Senior ASIC Design Engineer - RTL & SoC for Space Systems

WarmStart Ltd; Irvine, Northern (CA, KY); Hybrid; USD 150,000 - 210,000; Full time

Job summary

SpaceX is seeking a Senior ASIC Design Engineer to contribute to the Silicon Engineering team and develop next-generation ASICs for Starlink hardware. The role focuses on RTL implementation, verification, and timing closure, with collaboration across verification and physical design teams.

The ideal candidate has 5+ years of RTL experience and a strong background in high-speed, low-power ASIC design, earning opportunities tied to cutting-edge space infrastructure projects.

Qualifications

• Bachelor's degree in electrical engineering, computer engineering, or computer science.
• 5+ years of experience in RTL implementation.

Responsibilities

• Evaluate architectural trade-offs based on features, performance requirements, and system limitations.
• Define micro-architecture, implement RTL in Verilog/SystemVerilog, and deliver fully verified designs.
• Collaborate with verification team to ensure design coverage and verification.
• Provide timing constraints for IPs and support physical implementation in synthesis and timing.
• Participate in silicon bring-up and validation.

Skills

RTL implementation

ASIC/SoC integration

AXI/AHB protocols

EDA tools

Problem solving

Education

Bachelor's degree in EE/CE/CS

Tools

HDL simulators

HDL Lint tools

Job description

SpaceX is seeking a Senior ASIC Design Engineer to contribute to the Silicon Engineering team and develop next-generation ASICs for Starlink hardware. The role focuses on RTL implementation, verification, and timing closure, with collaboration across verification and physical design teams.

The ideal candidate has 5+ years of RTL experience and a strong background in high-speed, low-power ASIC design, earning opportunities tied to cutting-edge space infrastructure projects.