Senior RTL Design Engineer - Space-Grade ASICs

Spacex; Irvine (CA); Hybrid; USD 165,000 - 265,000; Full time

Benefits offered by this job

Stock options

Discretionary bonuses

Comprehensive medical vision dental

Job summary

SpaceX Irvine is seeking a Senior RTL Design Engineer to develop next‑generation ASICs for Starlink satellites and ground infrastructure. You will work with cross‑functional teams across systems, firmware, and ASIC implementation to deliver verified RTL in Verilog/SystemVerilog and ensure timing closure.

You will define micro-architecture, collaborate with verification, and participate in silicon bring‑up while solving clock-domain and power optimization challenges.

Qualifications

• Bachelor’s degree in electrical engineering, computer engineering, or computer science.
• 5+ years of experience in RTL implementation.
• Experience solving clock domain crossing and power optimization.
• Embedded CPU subsystems experience and familiarity with standard bus protocols (AXI, AHB).
• Experience with HDL simulators and HDL Lint tools.

Responsibilities

• Evaluate architectural trade-offs based on features, performance requirements and system limitations.
• Define micro-architecture, implement the RTL in Verilog/System Verilog, integrate that in top level and deliver the fully verified design.
• Work closely with verification team to ensure all aspects are covered and verified.
• Provide timing constraints for IPs and support the physical implementation team (synthesis, timing closure, formal check).
• Participate in silicon bring-up and validation.

Skills

RTL implementation

Clock domain crossings

Embedded CPU subsystems

High speed design

EDA tools

Team collaboration

Education

Bachelor's degree in Electrical/Computer Engineering or Computer Science

Tools

HDL simulators

HDL Lint tools

Job description

SpaceX Irvine is seeking a Senior RTL Design Engineer to develop next‑generation ASICs for Starlink satellites and ground infrastructure. You will work with cross‑functional teams across systems, firmware, and ASIC implementation to deliver verified RTL in Verilog/SystemVerilog and ensure timing closure.

You will define micro-architecture, collaborate with verification, and participate in silicon bring‑up while solving clock-domain and power optimization challenges.