Senior RTL Design Engineer for Space-Grade SoC

SpaceX; Palo Alto (CA); On-site; USD 175,000 - 280,000; Full time

Benefits offered by this job

Stock options

Long-term incentives

Medical, vision, and dental coverage

401(k) retirement plan

Paid vacation

Many paid holidays

Job summary

SpaceX is seeking a Senior RTL Design Engineer (Silicon Engineering) in California to develop next‑gen ASICs for Starlink and space networks. You will define architecture, write RTL in Verilog/SystemVerilog, and work with verification and physical teams to deliver timing‑clean designs.

Bachelor’s degree in EE/CE/CS and 5+ years RTL experience are required, with strengths in clock domain crossings, power optimization, and SoC integration; the role offers competitive compensation and stock options.

Qualifications

• Bachelor’s degree in electrical engineering, computer engineering, or computer science.
• 5+ years of experience in RTL implementation.

Responsibilities

• Evaluate architectural trade-offs based on features, performance requirements and system limitations.
• Define micro-architecture, implement the RTL in Verilog/System Verilog, integrate that in top level and deliver the fully verified, synthesis/timing clean design.
• Work closely with verification team to ensure all aspects of the design are covered and verified.
• Provide timing constraint for those IPs and support the physical implementation team (synthesis, timing closure, formality check).
• Participate in silicon bring-up and validation.

Skills

Clock domain crossings

Power optimization

SoC integration

Embedded CPU subsystems

Bus protocols (AXI/AHB)

High speed design

Low power design

Python scripting

EDA tools

HDL simulators

HDL lint

Team player

Learning on the job

Education

Bachelor’s degree in electrical engineering, computer engineering, or computer science

Tools

HDL simulators

HDL Lint tools

Job description

SpaceX is seeking a Senior RTL Design Engineer (Silicon Engineering) in California to develop next‑gen ASICs for Starlink and space networks. You will define architecture, write RTL in Verilog/SystemVerilog, and work with verification and physical teams to deliver timing‑clean designs.

Bachelor’s degree in EE/CE/CS and 5+ years RTL experience are required, with strengths in clock domain crossings, power optimization, and SoC integration; the role offers competitive compensation and stock options.