Senior RTL Design Engineer — Remote, SoC AI Workloads

Actalent; Santa Clara (CA); Remote; USD 200.000 - 500.000; Vollzeit

Zusammenfassung

Actalent, a global engineering services firm, seeks a Senior RTL Design Engineer to shape RTL for the Velaura SoC. You will design, implement, and optimize RTL, collaborating with architects and cross-disciplinary teams to deliver robust microarchitectures.

The role emphasizes performance/power/area optimization, memory/interconnect awareness, and hardware/software co-design with Verilog/SystemVerilog expertise. This is a fully remote role based in the United States with a Santa Clara, CA focus.

Qualifikationen

• Experience designing RTL for complex digital systems.
• Strong understanding of computer architecture, microarchitecture and digital design.
• Experience with Verilog/SystemVerilog and modern RTL design methodologies.
• Familiarity with performance, power, and area tradeoffs.
• Understanding of memory systems, interconnects, caches, DMA engines, or accelerator architectures.
• Experience with hardware/software co-design and system-level performance optimization.
• Strong debugging and problem-solving skills.
• Ability to work effectively in a collaborative, multidisciplinary engineering environment.

Aufgaben

• Design, implement, and optimize RTL for key portions of the Velaura SoC.
• Collaborate with architects to develop robust and efficient microarchitectures.
• Participate in hardware/software co-design discussions spanning AI workloads, memory systems, runtime software, and system architecture.
• Work with software teams to define hardware interfaces, execution flows, memory hierarchies, and performance-critical interactions.
• Contribute to compute engines, memory subsystems, interconnect fabrics, control processors, DMA engines, power-management logic, and other core SoC infrastructure.
• Optimize designs for performance, power, area, scalability, and reliability.
• Partner closely with verification and physical design teams throughout the development cycle.
• Analyze performance bottlenecks and propose architectural and implementation improvements.
• Leverage modern engineering tools, including AI-assisted development workflows, to improve productivity, quality, and design exploration.
• Participate in design reviews and contribute to a culture of technical excellence.

Kenntnisse

RTL design

Computer architecture

Verilog/SystemVerilog

Performance/power/area

Memory/interconnect

HW/SW co-design

Debugging

Collaborative work

Jobbeschreibung

Actalent, a global engineering services firm, seeks a Senior RTL Design Engineer to shape RTL for the Velaura SoC. You will design, implement, and optimize RTL, collaborating with architects and cross-disciplinary teams to deliver robust microarchitectures.

The role emphasizes performance/power/area optimization, memory/interconnect awareness, and hardware/software co-design with Verilog/SystemVerilog expertise. This is a fully remote role based in the United States with a Santa Clara, CA focus.