RTL Design Engineer

Delos Data; Palo Alto (CA); On-site; USD 160,000 - 240,000; Full time

Job summary

Delos Data is seeking a Senior RTL Design Engineer to design, implement, and deliver high-quality RTL for complex digital systems in our Palo Alto office. You will translate architectural specs into scalable microarchitectures using Verilog/SystemVerilog, collaborating with architecture, verification, and physical design teams to meet timing, power, and area goals.

Ideal candidates have 5+ years in RTL design, strong design fundamentals, and hands-on experience with synthesis, linting, and

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• 5+ years of experience in RTL design.
• Strong hands‑on experience with Verilog/SystemVerilog.
• Solid understanding of synchronous digital design and microarchitecture principles.
• Experience with simulation and debug tools (e.g., VCS, Questa, Verdi, DVE).
• Familiarity with synthesis, timing, and physical design constraints.
• Strong analytical and problem‑solving skills.
• Clear written and verbal communication skills for cross‑functional collaboration.
• High attention to detail and ability to deliver high‑quality design outcomes.
• Ability to work independently and manage tasks to completion, including AI‑assisted workflows.

Responsibilities

• Design and implement RTL for complex digital subsystems using Verilog/SystemVerilog.
• Translate architectural specifications into clean, efficient, and scalable microarchitectures.
• Collaborate with architecture, verification, and physical design teams to ensure design correctness and closure.
• Develop high-quality, reusable RTL with strong coding standards and documentation.
• Perform linting, CDC analysis, and ensure synthesis readiness of designs.
• Support integration and debug of RTL in simulation and early silicon environments.
• Participate in design reviews and provide technical input on architecture and implementation tradeoffs.
• Work with verification teams to ensure comprehensive functional coverage.
• Assist in timing closure and support backend teams as needed.
• Contribute to continuous improvement of design methodologies, flows, and tools.

Skills

RTL design

Verilog/SystemVerilog

Synchronous digital design

Cross-functional collaboration

Analytical and problem solving

Independent work

AI-assisted workflows

Education

Bachelor’s or Master’s degree in Electrical/Computer Engineering

Tools

VCS

Questa

Verdi

DVE

Job description

Who We Are

We are a startup building foundational technology to address performance, scalability, and resiliency challenges in large-scale AI data center clusters. We are backed by top-tier VC firms and notable angel investors.

Senior RTL Design Engineer

We are a startup building foundational technology to address performance, scalability, and resiliency challenges in large-scale AI data center clusters. We are backed by top-tier VC firms and notable angel investors.

The company is led by experienced builders and operators who have founded companies, taken them to scale, and exited successfully. We work with a strong sense of unity and shared responsibility, and we expect trust, integrity, and respect in how we collaborate and make decisions. We hold ourselves accountable to one another and to the quality of the work we deliver.

Headquartered in Silicon Valley, we operate across a mix of remote and on-site locations in the U.S. and Canada. We aim to create an environment where people are treated fairly, supported in their growth, and are empowered to do meaningful work alongside others who take the craft seriously.

What We Need

An experienced Senior RTL Design Engineer responsible for designing, implementing, and delivering high-quality RTL for complex digital systems. This role focuses on translating architectural specifications into scalable microarchitectures and production-ready RTL, with strong attention to performance, power, and area.

The ideal candidate has deep hands‑on experience with Verilog/SystemVerilog, strong digital design fundamentals, and experience working across the full design lifecycle in collaboration with architecture, verification, and physical design teams.

Key Responsibilities

• Design and implement RTL for complex digital subsystems using Verilog/SystemVerilog
• Translate architectural specifications into clean, efficient, and scalable microarchitectures
• Collaborate with architecture, verification, and physical design teams to ensure design correctness and closure
• Develop high-quality, reusable RTL with strong coding standards and documentation
• Perform linting, CDC analysis, and ensure synthesis readiness of designs
• Support integration and debug of RTL in simulation and early silicon environments
• Participate in design reviews and provide technical input on architecture and implementation tradeoffs
• Work with verification teams to ensure comprehensive functional coverage
• Assist in timing closure and support backend teams as neededContribute to continuous improvement of design methodologies, flows, and tools

Required Skills And Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field
• 5+ years of experience in RTL design
• Strong hands‑on experience with Verilog/SystemVerilog
• Solid understanding of synchronous digital design and microarchitecture principles
• Experience with simulation and debug tools (e.g., VCS, Questa, Verdi, DVE)
• Familiarity with synthesis, timing, and physical design constraints
• Strong analytical and problem‑solving skills
• Clear written and verbal communication skills for cross‑functional collaboration
• High attention to detail and ability to deliver high‑quality design outcomes
• Ability to work independently and manage tasks to completion, including AI‑assisted workflows

Desired Skills

• Experience designing high-performance systems (e.g., AI/ML accelerators, networking, or SoCs)
• Familiarity with low‑power design techniques (clock gating, power gating)
• Exposure to DFT concepts and design‑for‑test considerations
• Experience with scripting (Python, Tcl, or similar)
• Experience working in advanced semiconductor process nodes
• Experience using AI coding agents (e.g., Claude Code, Cursor, Copilot) in RTL workflows such a implementation, debug, and timing closure, with the rigor to verify AI-generated output
• Interest in turning design experience into reusable AI agent guidance, such as RTL coding patterns, timing‑closure playbooks, or review checklists

Compensation

Target base salary for this role is $160,000 - $240,000 per year, plus meaningful equity, benefits, and 401(k). Salary ranges are determined by role, level, experience, and location.

We are an equal opportunity employer. We value a range of perspectives and experiences and make employment decisions based on merit and business needs. We do not discriminate on the basis of legally protected characteristics.