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Delos Data Inc. is a remote-first startup building foundational AI data center technology in the US and Canada.
We seek an experienced RTL design engineer to design and implement RTL for complex subsystems, drive synthesis readiness, and assist in simulation and early silicon debugging. The ideal candidate has a Bachelor's or Master's in EE/CE with 5+ years RTL design experience, strong Verilog/SystemVerilog and microarchitecture skills, and hands-on experience with VCS, Questa, and Verdi.
We are a startup building foundational technology for AI data center clusters, backed by top-tier VC firms. We are a remote-first team of experienced builders based in the U.S. and Canada, with a culture of trust, integrity, and shared responsibility.