Senior Front-End CAD Engineer for RTL and Verification

Velaura; Santa Clara (CA); On-site; USD 200,000 - 300,000; Full time

Job summary

Velaura in Santa Clara, CA, is building custom silicon for Physical and Embodied AI. You will own the front end automation carrying RTL from entry to a clean handoff into DFT and implementation, covering RTL design flows, verification through prototyping, and AI-assisted tooling.

The ideal candidate has 8+ years in design verification or CAD, strong SystemVerilog RTL fluency, Python tooling experience, and Linux/EDA familiarity.

Qualifications

• 8+ years in design verification, design or CAD engineering
• Strong SystemVerilog/RTL fluency and ability to read/debug design and testbench code
• Hands-on experience building and running simulation and regression flows
• Excellent Python skills and a track record of building tools for engineers
• Working knowledge of front end EDA tools (Synopsys, Cadence, Siemens)
• Linux administration and distributed compute (LSF/Slurm), handling large regression workloads
• Familiarity with databases and dashboards (Grafana) for flow health and metrics
• Proven ability to support a live engineering flow with responsive issue turnaround

Responsibilities

• Own RTL design flows including build, lint, CDC and formal checks
• Own register generation and generator-driven flows for interfaces and integration
• Own DV flows including testbench build, regression execution and coverage collection
• Own emulation and FPGA prototyping build and bring-up
• Build and deploy AI-assisted tooling across design and verification workflows with compute/model access
• Maintain flows across the design cycle, manage tool versions and bug/upgrade requests
• Improve productivity and move proven workflows into standard practice
• Partner with DFT and physical design on handoff readiness and front end flows

Skills

SystemVerilog

RTL fluency

Python tooling

EDA tools

Linux admin

Regression flows

Debugging

Grafana

Communication

Tools

Python

LSF

Slurm

Grafana

Job description

Velaura in Santa Clara, CA, is building custom silicon for Physical and Embodied AI. You will own the front end automation carrying RTL from entry to a clean handoff into DFT and implementation, covering RTL design flows, verification through prototyping, and AI-assisted tooling.

The ideal candidate has 8+ years in design verification or CAD, strong SystemVerilog RTL fluency, Python tooling experience, and Linux/EDA familiarity.