Senior RTL Design Engineer (Remote, AI-Driven SoC)

Actalent; United States; Remote; USD 200,000 - 500,000; Full time

Benefits offered by this job

Medical, dental & vision

401(k) Retirement Plan

Life Insurance

Job summary

Actalent is seeking a Senior RTL Design Engineer to design and optimize RTL for the Velaura SoC. You will collaborate with architects, hardware and software teams to define interfaces, memory hierarchies, and performance-critical interactions, driving robust microarchitectures.

The role emphasizes hardware/software co-design, performance exploration, and using AI-assisted workflows to enhance productivity and design quality. Remote US-based position with competitive compensation.

Qualifications

• Experience designing RTL for complex digital systems.
• Strong understanding of computer architecture, microarchitecture, and digital design.
• Experience with Verilog/SystemVerilog and modern RTL design methodologies.
• Familiarity with performance, power, and area tradeoffs.
• Understanding of memory systems, interconnects, caches, DMA engines, or accelerator architectures.
• Experience with hardware/software co-design and system-level performance optimization.
• Strong debugging and problem-solving skills.
• Ability to work effectively in a collaborative, multidisciplinary engineering environment.

Responsibilities

• Design, implement, and optimize RTL for key portions of the Velaura SoC.
• Collaborate with architects to develop robust and efficient microarchitectures.
• Participate in hardware/software co-design discussions spanning AI workloads, memory systems, runtime software, and system architecture.
• Work with software teams to define hardware interfaces, execution flows, memory hierarchies, and performance-critical interactions.
• Contribute to compute engines, memory subsystems, interconnect fabrics, control processors, DMA engines, power-management logic, and other core SoC infrastructure.
• Optimize designs for performance, power, area, scalability, and reliability.
• Partner closely with verification and physical design teams throughout the development cycle.
• Analyze performance bottlenecks and propose architectural and implementation improvements.
• Leverage modern engineering tools, including AI-assisted development workflows, to improve productivity, quality, and design exploration.
• Participate in design reviews and contribute to a culture of technical excellence.

Skills

RTL design

Computer architecture

Verilog/SystemVerilog

Perf/Power/Area

Memory systems

HW/SW co-design

Debugging

Collaboration

Tools

AI tools

FPGA prototyping

Emulation

Silicon bring-up

Job description

Actalent is seeking a Senior RTL Design Engineer to design and optimize RTL for the Velaura SoC. You will collaborate with architects, hardware and software teams to define interfaces, memory hierarchies, and performance-critical interactions, driving robust microarchitectures.

The role emphasizes hardware/software co-design, performance exploration, and using AI-assisted workflows to enhance productivity and design quality. Remote US-based position with competitive compensation.