Front-End CAD Engineer: RTL & AI Tooling Leader

Velaura AI, Inc.; Santa Clara (CA); Presencial; USD 200.000 - 300.000; Jornada completa

Descripción de la vacante

Velaura AI, Inc. seeks a front-end automation engineer to own RTL design flows, register generation, and DV/AI-assisted tooling across the design-to-handoff cycle. You will collaborate with CAD and Engineering Infrastructure to ensure scalable, upgrade-friendly flows through RTL to DFT and implementation.

You will drive simulation, regression, and coverage, and mentor teams in using AI-assisted tooling to improve productivity and flow health across projects in a cutting-edge silicon environment.

Formación

• 8+ years in design verification, design or CAD engineering.
• Proficiency in SystemVerilog and reading/debugging RTL and testbenches.
• Experience building and running simulation and regression flows.

Responsabilidades

• Own RTL design flows: build, lint, CDC and formal checks.
• Own register generation and generator-driven flows for interfaces.
• Own DV flows: testbench build, regression execution and coverage collection.
• Own emulation and FPGA prototyping build and bring up.
• Build and deploy AI-assisted tooling across design/verification workflows.
• Maintain flows across the design cycle and manage tool versions.

Conocimientos

SystemVerilog RTL fluency

Python scripting

Front end design/verification

Linux admin & distributed compute

EDA tools (Synopsys/Cadence/Siemens)

Grafana dashboards

Herramientas

LSF/Slurm

Descripción del empleo

Velaura AI, Inc. seeks a front-end automation engineer to own RTL design flows, register generation, and DV/AI-assisted tooling across the design-to-handoff cycle. You will collaborate with CAD and Engineering Infrastructure to ensure scalable, upgrade-friendly flows through RTL to DFT and implementation.

You will drive simulation, regression, and coverage, and mentor teams in using AI-assisted tooling to improve productivity and flow health across projects in a cutting-edge silicon environment.