Advanced FPGA/ASIC Design Engineer for Space Systems

Spacex; Irvine (CA); Hybrid; USD 125,000 - 195,000; Full time

Benefits offered by this job

Stock options

401(k) plan

Medical, vision, dental

Paid parental leave

Paid time off

Employee discounts

Job summary

SpaceX in Irvine, CA is seeking an FPGA/ASIC Design Engineer (Silicon Engineering) to craft next‑gen FPGAs and ASICs for Starlink. You will work with cross‑functional teams across systems, firmware, design, and validation to deliver high‑impact silicon.

You should have 1+ years of RTL design with SystemVerilog/Verilog/VHDL and a strong EE foundation. SpaceX offers extensive benefits, stock options, and a collaborative, fast‑paced environment.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or Physics.
• 1+ years of RTL Design experience in SystemVerilog, Verilog or VHDL.

Responsibilities

• Design ASICs and/or FPGAs for Starlink projects, implementing complex SoC blocks and SoC integration tasks using Verilog/System Verilog
• Optimize designs for power, performance and area
• Participate in the full ASIC/FPGA design lifecycle for Starlink projects, from high-level conceptual and architectural discussions through microarchitecture, design partitioning, and collaboration with backend/implementation teams, and assist in lab bring-up and validation
• Contribute to continual improvements to our designs by building physical and digital tools to analyze data collected on orbit and in the lab
• Engage in high-level architectural design for test systems to support FPGA/ASIC validation, generational interoperability, and integration with DSP/communications subsystems for comprehensive lab and on-orbit verification
• Collaborate with software engineers in developing production software for your designs

Skills

Python

C/C++

Bash

SystemVerilog

Verilog

VHDL

AXI/AHB/APB

EDA tools

Electrical fundamentals

PCB debugging

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or Physics

Master's in Electrical/Computer Engineering or related field

Tools

HDL simulators (VCS, Questa, IES)

HDL Lint (Spyglass)

Xilinx Vivado

Altera Quartus II

Job description

SpaceX in Irvine, CA is seeking an FPGA/ASIC Design Engineer (Silicon Engineering) to craft next‑gen FPGAs and ASICs for Starlink. You will work with cross‑functional teams across systems, firmware, design, and validation to deliver high‑impact silicon.

You should have 1+ years of RTL design with SystemVerilog/Verilog/VHDL and a strong EE foundation. SpaceX offers extensive benefits, stock options, and a collaborative, fast‑paced environment.