Senior ASIC PD Engineer for TPU AI Hardware & PPA

Google; Sunnyvale (CA); On-site; USD 163,000 - 236,000; Full time

Benefits offered by this job

Bonus target

Equity

Benefits

Job summary

Google is seeking an ASIC Physical Design Engineer in Sunnyvale to shape AI/ML hardware acceleration. You will drive TPU architecture and collaborate with RTL, DFT, Floorplan, and signoff teams to optimize power, performance, and area across complex digital designs.

You will join a team delivering cutting-edge silicon for Google's TPU and AI workloads, with a focus on design verification, back-end flows, and engineering rigor in a fast-paced hyperscale environment.

Qualifications

• Bachelor's degree or equivalent practical experience in a related field.
• 7 years of experience with physical design from RTL to GDSII and timing closure.
• Experience with Python, Tcl, or Perl scripting.

Responsibilities

• Participate in the physical design of complex blocks and full chip closure.
• Collaborate with RTL, DFT, Floorplan, and full-chip Signoff teams to optimize PPA.
• Support design verification and integration of TPU architecture within AI/ML systems.

Skills

Python

Tcl

Perl

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Tools

Synopsys/Cadence PnR tools

Backend flows (LEC, PI/SI, DRC/LVS)

Job description

Google is seeking an ASIC Physical Design Engineer in Sunnyvale to shape AI/ML hardware acceleration. You will drive TPU architecture and collaborate with RTL, DFT, Floorplan, and signoff teams to optimize power, performance, and area across complex digital designs.

You will join a team delivering cutting-edge silicon for Google's TPU and AI workloads, with a focus on design verification, back-end flows, and engineering rigor in a fast-paced hyperscale environment.