Senior RTL Design Engineer, TPU

Google; Sunnyvale (CA); On-site; USD 163,000 - 236,000; Full time

Job summary

Google is seeking an experienced ASIC Design Engineer to help shape the future of AI/ML hardware acceleration. You will contribute to TPU architecture and its integration in AI/ML systems, designing RTL IP with a focus on management and control subsystems for datacenter accelerators.

You will collaborate across software and hardware teams, driving RTL development and verification for cutting-edge silicon used in Google's TPU technology.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field, or equivalent practical experience.
• 8 years of experience in ASIC design.
• Experience with SystemVerilog/RTL coding.
• Experience with scripting languages (e.g., Tcl, Python or Perl).

Responsibilities

• Create and review management and control subsystem's design microarchitecture specifications.
• Develop SystemVerilog RTL to implement logic for ASIC products according to established coding and quality guidelines.
• Work with architecture and power teams to evaluate features and their impact.
• Work with design validation (DV) teams to create test plans to verify, and debug design RTL.
• Work with physical design teams to ensure design meets physical requirements and timing closure.

Skills

ASIC design experience

SystemVerilog/RTL coding

Scripting languages (Tcl, Python or Pi

Education

Bachelor's degree in Electrical/Computer Engineering or Computer Science

Tools

SystemVerilog

Job description

In most instances, this position requires in-person interviews as part of the hiring process.

Minimum qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 8 years of experience in ASIC design.
• Experience with SystemVerilog/RTL coding.
• Experience with scripting languages (e.g., Tcl, Python or Perl).

Preferred qualifications

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Experience interacting with software, system hardware, and other cross-functional teams.
• Experience with chip management, clocking, reset, and peripherals like I2C, SPI, UART, etc.
• Understanding of digital design fundamentals, including synchronous and asynchronous logic, state machines and bus protocols.

About the job

In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

In this role, you will join a team working on SoC-level RTL design for our data center accelerators. You will design RTL Intellectual Property (IP) with the focus on management and control subsystem, also participate in developing infrastructure and methodology that form the foundation of our SoCs (i.e., clocking, reset, error handling, debug, chip management and SOC chassis etc.). You will build a global understanding of how our accelerators are built from concept to production. This is a highly cross-functional role that will require you to coordinate and co-design with our software and system hardware counterparts. You will utilize, a background in RTL design, and the ability to lead to multi-faceted efforts involving many stakeholders.

The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving team behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $163000 - $236000 (USD) + 15% bonus target + equity + benefits

Responsibilities

Learn more about benefits at Google .

• Work separately to create and review management and control subsystem's design microarchitecture specifications.
• Develop SystemVerilog RTL to implement logic for ASIC products according to established coding and quality guidelines.
• Work with architecture and power teams to evaluate features and their impact.
• Work with design validation (DV) teams to create test plans to verify, and debug design RTL.
• Work with physical design teams to ensure design meets physical requirements and timing closure.

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .