Senior RTL Design Engineer for AI Accelerator ASIC

Precision Labs; Texas; Hybrid; USD 120,000 - 200,000; Full time

Benefits offered by this job

Medical insurance

Dental & Vision

HSA employer contribution

Gym/Well-being benefits

Headspace subscription

Job summary

SambaNova Systems is seeking an RTL Design Engineer to contribute to the Reconfigurable Dataflow Unit (RDU) ASICs behind our AI acceleration platforms. You will own blocks within a subsystem, write and debug RTL, and guide them through implementation, tape-out and silicon bring-up with senior engineers.

Ideal candidates have a strong foundation in digital logic, SystemVerilog, and computer architecture, plus experience trading off power, performance and area.

Qualifications

• B.S. in Electrical Engineering, Computer Engineering, or Computer Science.
• 5+ years of experience in ASIC RTL design.
• Strong SystemVerilog RTL design skills for high‑speed ASICs.
• Experience trading off power, performance and area.
• Knowledge of AXI, PCIe, Ethernet, and HBM or DDR interconnects.
• Experience with RTL linting, CDC and LEC.

Responsibilities

• Own blocks within a larger RTL subsystem for the RDU ASICs.
• Write and debug RTL and carry blocks through implementation.
• Guide designs through tape‑out and silicon bring‑up.
• Collaborate with principal engineers, design verification and physical design.

Skills

SystemVerilog RTL design

Digital logic design

Computer architecture

Python scripting

Linux shell

Git

Clock domain crossing

Education

Bachelor's in Electrical/Computer Engineering or CS

M.S. or Ph.D. in EE/CE/CS

Tools

Digital logic synthesis tools

Static timing analysis tools

Linting/CDC/LEC tools

Job description

SambaNova Systems is seeking an RTL Design Engineer to contribute to the Reconfigurable Dataflow Unit (RDU) ASICs behind our AI acceleration platforms. You will own blocks within a subsystem, write and debug RTL, and guide them through implementation, tape-out and silicon bring-up with senior engineers.

Ideal candidates have a strong foundation in digital logic, SystemVerilog, and computer architecture, plus experience trading off power, performance and area.