Principal RTL Design Engineer — RDU Block Lead

SambaNova; San Jose (CA); On-site; USD 180,000 - 255,000; Full time

Benefits offered by this job

Health insurance

Dental insurance

Vision insurance

HSA with employer contribution

Gym/Wellness benefits

Job summary

SambaNova is seeking a Principal RTL Design Engineer to own the microarchitecture and RTL for the next-generation Reconfigurable Dataflow Unit (RDU). This senior individual contributor role requires taking a block from microarchitecture specification through tape-out, balancing power, performance, and area while meeting aggressive frequency targets.

You will write, integrate, and debug synthesizable SystemVerilog RTL, own PPA, and collaborate with verification, architects, and software teams to

Qualifications

• B.S. in Electrical Engineering, Computer Engineering, or Computer Science.
• 7+ years of industry experience in ASIC RTL design.
• Mastery of synthesizable SystemVerilog for high-speed ASICs, including SVA.
• High-frequency design experience for aggressive frequency targets.
• Foundational knowledge of computer architecture, digital logic, memory structures.
• Ownership of a complex block from microarchitecture through tape-out on production ASIC.
• Experience converging power, performance, and area with floorplanning and timing feedback.
• Scripting in Python for design and flow automation.

Responsibilities

• Own microarchitecture and RTL for a major block or subsystem from specification through tape-out.
• Write, integrate, and debug synthesizable SystemVerilog RTL through full chip implementation.
• Own PPA for your area, achieving aggressive frequency targets through pipeline and retiming.
• Drive timing closure and design quality: synthesis, STA, lint, CDC, LEC, and SVAs.
• Partner with design verification to define verification intent and coverage.
• Collaborate with architects and software teams to prototype performance features.
• Drive AI, automation, and new EDA tool methodologies in the design flow.
• Set the technical bar in design reviews and mentor engineers.

Skills

SystemVerilog

RTL design

Python scripting

PPA optimization

High-frequency design

Clock domain crossing

Digital logic design

Education

B.S. in Electrical/Computer Engineering or CS

M.S./Ph.D. preferred

Job description

SambaNova is seeking a Principal RTL Design Engineer to own the microarchitecture and RTL for the next-generation Reconfigurable Dataflow Unit (RDU). This senior individual contributor role requires taking a block from microarchitecture specification through tape-out, balancing power, performance, and area while meeting aggressive frequency targets.

You will write, integrate, and debug synthesizable SystemVerilog RTL, own PPA, and collaborate with verification, architects, and software teams to