Senior RTL Design Engineer for AI Accelerator ASIC

SambaNova; San Jose (CA); On-site; USD 120,000 - 200,000; Full time

Benefits offered by this job

Health insurance

HSA

Dental

Vision

Disability insurance

Life insurance

AD&D

Flexible Spending Account

Headspace membership

Gympass+

One Medical

Employee Assistance Program

Job summary

SambaNova RTL Design Engineers build blocks of the Reconfigurable Dataflow Unit (RDU) ASICs behind our AI acceleration systems. You’ll own blocks within a larger subsystem, contribute sections of the microarchitecture, write and debug RTL, and carry your blocks through implementation, tape-out, and silicon bring-up.

You’ll work with principal engineers, design verification, and physical design teams, taking on larger blocks as you deepen architectural depth.

Qualifications

• BS in Electrical Engineering, Computer Engineering, or Computer Science.
• 5+ years of experience in ASIC RTL design.
• Solid foundation in computer architecture and digital logic design.
• Strong SystemVerilog RTL design skills for high-speed, high-performance ASICs.
• Experience making design decisions that trade off power, performance, and area.
• Knowledge of AXI, PCIe, Ethernet, and HBM or DDR interconnects.
• Experience with digital logic synthesis tools and static timing analysis.
• Proficiency with linting, clock-domain crossing, and formal checks.
• Experience implementing SystemVerilog Assertions to check design intent.
• Familiarity with hardware performance analysis tools and tuning.
• Familiarity with Git for release cycles.
• Python and Linux shell scripting experience.

Responsibilities

• Own blocks within a larger subsystem and contribute RTL design.
• Write and debug RTL and carry blocks through implementation.
• Collaborate across teams through tape-out and silicon bring-up.

Skills

ASIC RTL design

SystemVerilog

Computer architecture

Digital logic design

Power/performance/area trade-offs

Interconnects & protocols (AXI/PCIe/Eh

Synthesis tools & timing analysis

Linting/Clock domain crossing/ formal

SystemVerilog Assertions

Hardware performance tools

Git

Python & Linux shell

Education

B.S. in Electrical Engineering, Computer Engineering, or Computer Science

Tools

SystemVerilog

Job description

SambaNova RTL Design Engineers build blocks of the Reconfigurable Dataflow Unit (RDU) ASICs behind our AI acceleration systems. You’ll own blocks within a larger subsystem, contribute sections of the microarchitecture, write and debug RTL, and carry your blocks through implementation, tape-out, and silicon bring-up.

You’ll work with principal engineers, design verification, and physical design teams, taking on larger blocks as you deepen architectural depth.