Senior RTL Design Architect for High-Performance SoCs

AMD; San Jose (CA); Hybrid; USD 140,000 - 210,000; Full time

Benefits offered by this job

AMD benefits at a glance

Job summary

AMD's FPGA Product and Platform development team in San Jose, CA is seeking a skilled engineer to drive RTL design and implementation for complex digital blocks. You will work across physical design, verification, and software tooling to deliver silicon and first-time-right software solutions.

You will design RTL using Verilog/SystemVerilog, support synthesis, place-and-route, and STA, and collaborate with global teams across time zones. Strong scripting in Python/Perl/Tcl is valued.

Qualifications

• Bachelor's or master's degree in electrical or computer engineering.
• Strong RTL design and integration experience using Verilog and SystemVerilog.
• Experience with high-speed interfaces and complex IPs (HBM, PCIe, SerDes).
• Familiarity with industry EDA tools and design automation.

Responsibilities

• Participate in all stages of the design flow from RTL development through GDS implementation.
• Design and implement RTL for complex digital/mixed-signal blocks using Verilog and SystemVerilog.
• Support physical design activities: synthesis, DFT implementation, place-and-route, STA.
• Collaborate with verification teams using UVM, constrained-random testing, and BFMs.
• Develop and maintain design automation tooling with Python, Tcl, Shell, and Perl.

Skills

RTL Design

Verilog/SystemVerilog

DFT/STA

UVM verification

Scripting (Python, Perl, Tcl, Shell)

Synthesis & STA

Cross-functional collaboration

Education

Bachelor's or Master's in Electrical/Computer Engineering

Tools

Synopsys DFT Compiler

TestMAX

PrimeTime

VCS

Cadence tool suites

Job description

AMD's FPGA Product and Platform development team in San Jose, CA is seeking a skilled engineer to drive RTL design and implementation for complex digital blocks. You will work across physical design, verification, and software tooling to deliver silicon and first-time-right software solutions.

You will design RTL using Verilog/SystemVerilog, support synthesis, place-and-route, and STA, and collaborate with global teams across time zones. Strong scripting in Python/Perl/Tcl is valued.