Senior RTL Design Engineer — AI-Driven Silicon & FPGA

Advanced Micro Devices, Inc.; San Jose (CA); Hybrid; USD 140,000 - 190,000; Full time

Job summary

AMD is seeking a passionate HW architect for FPGA/ASIC efforts in our San Jose hybrid environment. You will drive RTL design and verification for advanced IP blocks, work with DFT implementations, and collaborate across global teams to meet milestones.

You should have strong Verilog/SystemVerilog skills, experience with EDA tools, and a solid foundation in ASIC/SoC development, including timing, floorplanning, and test.

Qualifications

• Experience across RTL architecture to physical implementation.
• Proficient in Verilog/SystemVerilog for complex blocks.
• Strong background with high-speed interfaces and IPs (HBM, PCIe, SerDes).
• Knowledge of DFT, LBIST, MBIST, boundary scan, and related test tech.

Responsibilities

• Participate in RTL development through GDS; implement RTL for complex blocks.
• Support synthesis, place-and-route, STA and physical design activities.
• Collaborate with verification teams using SystemVerilog/UVM.
• Develop and maintain design automation scripts (Perl, Tcl, Python).
• Coordinate with cross-functional teams across time zones and locations.

Skills

RTL design

Verilog

SystemVerilog

Python

UVM

scripting (Perl/Tcl/Shell)

Education

Bachelor's or Master's in Electrical/Computer Engineering

Tools

Synopsys DFT Compiler

PrimeTime

VCS

TestMAX

Cadence tool suites

DFT/Verification tools

Job description

AMD is seeking a passionate HW architect for FPGA/ASIC efforts in our San Jose hybrid environment. You will drive RTL design and verification for advanced IP blocks, work with DFT implementations, and collaborate across global teams to meet milestones.

You should have strong Verilog/SystemVerilog skills, experience with EDA tools, and a solid foundation in ASIC/SoC development, including timing, floorplanning, and test.