Lead RTL Architect for AI Accelerator Silicon

DensityAI, Inc.; Mountain View (CA); On-site; USD 180,000 - 300,000; Full time

Benefits offered by this job

Equity grant

Medical/dental/vision insurance

401(k)

Standard PTO

Job summary

DensityAI, Inc. is seeking an experienced RTL design engineer to architect and implement digital blocks for its AI accelerator.

You’ll translate microarchitecture specifications into synthesizable SystemVerilog RTL, own the datapath, interconnect, and control logic, and drive design quality from RTL to tapeout. You will collaborate with DV, PD, and DFT teams to ensure timing closures, power efficiency, and robust testability, leveraging scripting to streamline flows.

Qualifications

• Strong digital-design fundamentals and expert Verilog/SystemVerilog RTL.
• 5+ years designing complex digital blocks/SoCs taken to silicon.
• Solid microarchitecture skills — pipelining, datapath/control, FIFOs, arbitration.
• Synthesis & timing awareness — writing synthesizable RTL, SDC constraints, STA, clock/power gating.
• Collaboration with DV, PD, and DFT across RTL2GDS flow to tapeout.
• Python/Tcl scripting for design automation.

Responsibilities

• Own RTL design of digital blocks/subsystems for our accelerator.
• Translate architectural specs into efficient, synthesizable RTL meeting PPA targets.
• Drive microarchitecture trade-offs for high performance and low power design.
• Partner with DV on verification, PD on synthesis/timing, and DFT on testability.
• Own block-level quality: synthesis, timing constraints, lint, CDC signoff.
• Contribute to architecture definition and design reviews; debug across simulations and silicon bring-up.
• Use AI-assisted tool flows to accelerate design and verification.

Skills

Verilog/SystemVerilog RTL

Digital block design

Microarchitecture design

Synthesis & timing

Power/area optimization

Python/Tcl scripting

Team collaboration with DV/PD/DFT

NoC/memory subsystems

Tools

HBM

PCIe

SerDes

RISC‑V/CPU

FPGA prototyping

Job description

DensityAI, Inc. is seeking an experienced RTL design engineer to architect and implement digital blocks for its AI accelerator.

You’ll translate microarchitecture specifications into synthesizable SystemVerilog RTL, own the datapath, interconnect, and control logic, and drive design quality from RTL to tapeout. You will collaborate with DV, PD, and DFT teams to ensure timing closures, power efficiency, and robust testability, leveraging scripting to streamline flows.