Senior RTL Architect for AI Accelerator Hardware

River AI Inc.; Palo Alto, Austin (CA, TX); On-site; USD 200,000 - 420,000; Full time

Benefits offered by this job

Health benefits

Dental benefits

Vision benefits

Unlimited PTO

Relocation support

Job summary

River AI Inc. is seeking exceptional RTL design engineers to architect and implement high-performance AI accelerator hardware.

You will define architecture, micro-architecture, and implementation for SoCs on advanced nodes, owning large parts of the chip and coordinating with compiler, performance model, verification, and physical design teams. Based in Austin or Palo Alto, you will collaborate across stacks to optimize throughput, latency, and power, contribute to ECOs and silicon-at-scale

Qualifications

• Bachelor’s degree in Electrical Engineering or Computer Engineering with at least 5+ years of hands-on industry experience on advanced process nodes (7nm or below).
• Deep hands-on proficiency with RTL, synthesis, physical design, and timing tools (SystemVerilog, VCS/Verdi, Fusion Compiler, PrimeTime).
• Proven track record delivering functional and performant silicon at scale, including ECOs.

Responsibilities

• Create high-level architectural specifications and detailed micro-architectural designs for AI hardware subsystems.
• Design and implement complex logic using SystemVerilog with focus on pipelines, throughput vs latency, and power-efficient data paths.
• Collaborate with backend, verification, and physical design teams to drive synthesis, floorplanning, STA, and timing fixes.
• Work with compiler, performance modeling, and software groups to identify bottlenecks across the full stack.

Skills

Architectural knowledge

Collaborative mindset

C/C++/Python

AI accelerators / SoCs

Education

Bachelor's degree in Electrical Engineering or Computer Engineering

Tools

System Verilog

VCS/Verdi

Fusion Compiler

PrimeTime

Job description

River AI Inc. is seeking exceptional RTL design engineers to architect and implement high-performance AI accelerator hardware.

You will define architecture, micro-architecture, and implementation for SoCs on advanced nodes, owning large parts of the chip and coordinating with compiler, performance model, verification, and physical design teams. Based in Austin or Palo Alto, you will collaborate across stacks to optimize throughput, latency, and power, contribute to ECOs and silicon-at-scale