Senior RTL Design Engineer for AI Accelerator ASIC

Socket.dev; Austin (TX); On-site; USD 120,000 - 200,000; Full time

Benefits offered by this job

Health insurance

Dental & Vision

HSA

Equity/Stock options

Headspace

Gympass+

Job summary

SambaNova Systems in Austin, TX, is seeking an experienced RTL Design Engineer to contribute blocks within the RDU ASICs for AI acceleration systems. You will implement, test, and optimize SystemVerilog blocks through implementation, tape-out, and silicon bring-up in collaboration with senior engineers and design teams.

The role requires a strong foundation in digital logic, computer architecture, and high-speed ASIC design, with hands-on RTL coding, SVA checks, and experience using linting,

Qualifications

• B.S. in Electrical/Computer Engineering or Computer Science.
• 10?
• 5+ years of ASIC RTL design experience.
• Strong SystemVerilog RTL design for high-speed ASICs.
• Knowledge of AXI, PCIe, Ethernet, and HBM/DDR interconnects.
• Experience with RTL linting, STA, and CDC checks.
• Proficiency with Git, Python, and Linux shell.

Responsibilities

• Own blocks within the Reconfigurable Dataflow Unit (RDU) ASICs.
• Write and debug RTL and contribute to microarchitecture specs.
• Carry blocks through implementation, tape-out and silicon bring-up.
• Collaborate with principal engineers, design verification, and physical design.

Skills

SystemVerilog RTL design

Digital logic design

Computer architecture

Power–perf–area trade-offs

Interconnect protocols AXI PCIeEther

RTL debugging

Scripting Python

Linux shell

Git version control

Education

Bachelor's in EE/CE/CS

MS/PhD preferred

Tools

Synthesis tools

Static timing analysis tools

Linting/CDC tooling

Simulation tools

Job description

SambaNova Systems in Austin, TX, is seeking an experienced RTL Design Engineer to contribute blocks within the RDU ASICs for AI acceleration systems. You will implement, test, and optimize SystemVerilog blocks through implementation, tape-out, and silicon bring-up in collaboration with senior engineers and design teams.

The role requires a strong foundation in digital logic, computer architecture, and high-speed ASIC design, with hands-on RTL coding, SVA checks, and experience using linting,