Senior RTL Design Engineer - AI Accelerator Block

SambaNova; Austin (TX); On-site; USD 180,000 - 255,000; Full time

Benefits offered by this job

Equity

Health insurance

HSA with employer contribution

Job summary

SambaNova is seeking a Principal RTL Design Engineer to own the microarchitecture and RTL for the next-generation Reconfigurable Dataflow Unit (RDU). This senior IC role requires delivering from spec through tape-out, balancing power, performance, and area while meeting aggressive frequency targets.

You will write and debug SystemVerilog RTL, own PPA, and collaborate with verification, architects, and software teams to drive performance improvements and design quality.

Qualifications

• BS in Electrical Engineering, Computer Engineering, or Computer Science.
• 7+ years of industry experience in ASIC RTL design.
• Mastery of synthesizable SystemVerilog and SVA to capture design intent.
• High-frequency design experience with datapath pipelining and timing targets.
• Strong foundation in computer architecture, digital logic, and memory structures.
• Experience delivering blocks from microarchitecture through tape-out on production ASIC.

Responsibilities

• Own the microarchitecture and RTL for a major RDU block from spec to tape-out.
• Write, integrate, and debug synthesizable SystemVerilog RTL for full chip implementation.
• Own PPA for your area, achieving aggressive frequency targets.
• Drive timing closure and design quality including lint, CDC, LEC, and STA.
• Partner with verification to define verification intent and coverage.
• Work with architects and software to prototype features improving performance.
• Drive AI, automation, and new EDA tool methodologies in the design flow.
• Set the technical bar in design reviews and mentor engineers.

Skills

SystemVerilog

SVA

RTL design

Synthesis

STA

Python

Microarchitecture

Digital design

Lint

CDC

LEC

PPA optimization

Education

B.S. in Electrical Engineering, Computer Engineering, or Computer Science

M.S. in Electrical Engineering, Computer Engineering, or Computer Science

Tools

AXI

PCIe

Ethernet

HBM

DDR

Job description

SambaNova is seeking a Principal RTL Design Engineer to own the microarchitecture and RTL for the next-generation Reconfigurable Dataflow Unit (RDU). This senior IC role requires delivering from spec through tape-out, balancing power, performance, and area while meeting aggressive frequency targets.

You will write and debug SystemVerilog RTL, own PPA, and collaborate with verification, architects, and software teams to drive performance improvements and design quality.