Senior ASIC RTL Design Engineer

Advanced Micro Devices; San Jose (CA); On-site; USD 180,000 - 280,000; Full time

Job summary

AMD in San Jose, CA seeks a Senior ASIC Design Engineer to own the RTL design lifecycle for cutting-edge IP blocks, driving from specification to production silicon.

The ideal candidate has extensive Verilog RTL coding experience, strong timing closure skills, and a track record of multiple production tape-outs. You will mentor junior engineers and collaborate across architecture, verification, and physical design teams.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering or Computer Engineering.
• Proven track record with 2+ production ASIC tape-outs in senior design roles.
• Expert-level Verilog RTL coding skills with deep understanding of synthesizable RTL constructs.
• Experience with RTL → Synthesis → STA → Physical Design → Tape-out workflow.

Responsibilities

• RTL Design & Microarchitecture: Author detailed micro-architecture specifications and own complete Verilog RTL implementation of major IP blocks, ensuring compliance with PPA targets and timing requirements.
• Full ASIC Development Lifecycle: Drive design from concept through production silicon across all phases: specification, RTL coding, lint/CDC checks, synthesis, timing analysis, verification, physical design integration, and post-silicon validation.
• Timing Closure & Optimization: Develop and maintain timing constraints (SDC), perform static timing analysis (STA) using industry-standard tools (PrimeTime/Tempus), resolve timing violations, and collaborate with physical design to achieve timing closure.
• SOC Integration: Integrate complex ASIC IP blocks into full-chip SOC environment, ensuring proper connectivity, clock domain crossings, and interface compliance with industry-standard protocols (AMBA AXI/AHB/APB, PCIe, CXL).
• Design Quality & Verification: Partner with verification teams to ensure comprehensive functional coverage; implement design-for-test (DFT) and design-for-debug (DFD) features; participate in RTL quality reviews and signoff.
• Physical Design Collaboration: Work closely with physical design engineers on floorplanning, placement constraints, clock tree synthesis, and power grid design to ensure timing convergence and manufacturing readiness.
• Automation & Productivity: Develop Python/Perl/Tcl scripts to automate repetitive tasks, improve design quality checks, and enhance team efficiency throughout the design flow.
• Cross‑Functional Collaboration: Engage with architecture, verification, physical design, CAD, and post-silicon teams to resolve complex technical challenges and deliver high‑quality silicon on schedule.

Skills

Verilog RTL coding

Timing closure

Mentoring

Cross‑functional collaboration

Python scripting

Education

Bachelor's or Master's in Electrical/Computer Engineering

Tools

PrimeTime

Tempus

Synthesis tools

Job description

AMD in San Jose, CA seeks a Senior ASIC Design Engineer to own the RTL design lifecycle for cutting-edge IP blocks, driving from specification to production silicon.

The ideal candidate has extensive Verilog RTL coding experience, strong timing closure skills, and a track record of multiple production tape-outs. You will mentor junior engineers and collaborate across architecture, verification, and physical design teams.