Senior RTL Architect for AI Accelerator (Equity Eligible)

DensityAI; Mountain View (CA); On-site; USD 250,000 - 375,000; Full time

Benefits offered by this job

Equity grant

Medical / dental / vision

401(k)

PTO

Job summary

DensityAI is seeking a seasoned RTL design engineer to own the design of digital blocks for our AI accelerator. You will oversee microarchitecture, SystemVerilog implementation, and integration, translating architectural specs into synthesizable RTL that meets PPA targets.

You will collaborate with DV, PD, and DFT teams across the RTL2GDS flow to tape out silicon, while leveraging Python/Tcl for automation and tackling advanced interconnects and memory subsystems.

Qualifications

• 5+ years designing complex RTL blocks or SoCs to silicon.
• Strong Verilog/SystemVerilog RTL and microarchitecture skills.
• Experience with synthesis, timing, constraints (SDC/STA) and lint.
• Collaborates with DV, PD, and DFT across RTL2GDS flow to tapeout.
• Proficient in scripting for design automation (Python/Tcl).
• Knowledge of high-speed interfaces (HBM, PCIe, SerDes) is a plus.

Responsibilities

• Own RTL design of digital blocks/subsystems for the accelerator.
• Translate specs into efficient, synthesizable RTL meeting PPA targets.
• Drive microarchitecture tradeoffs for high performance and low power.
• Partner with DV, PD, and DFT across verification and timing flows.
• Ensure block-level quality: constraints, lint, CDC, and timing signoff.
• Contribute to architecture reviews and silicon bring-up delays.
• Develop and extend AI-assisted tool flows for design/verification.

Skills

RTL design

SystemVerilog

Microarchitecture

Synthesis/Timing

Python/Tcl scripting

DV/verification collaboration

Tools

HBM

PCIe

SerDes

Job description

DensityAI is seeking a seasoned RTL design engineer to own the design of digital blocks for our AI accelerator. You will oversee microarchitecture, SystemVerilog implementation, and integration, translating architectural specs into synthesizable RTL that meets PPA targets.

You will collaborate with DV, PD, and DFT teams across the RTL2GDS flow to tape out silicon, while leveraging Python/Tcl for automation and tackling advanced interconnects and memory subsystems.