Senior RTL Architect — L1 Accelerator ASIC

Ericsson GmbH; Austin (TX); Hybrid; USD 117,000 - 175,000; Full time

Benefits offered by this job

Health benefits

401(k) plan

Paid time off

Parental leave

Job summary

Ericsson’s Accelerator IP team in Austin, TX is seeking a Senior RTL Design Engineer to own the microarchitecture of next-generation L1 accelerators from concept to silicon, translating DSP/FEC algorithms into high-performance SystemVerilog.

You will lead major IP blocks end-to-end, drive power/area/throughput trade-offs, and collaborate across verification, backend, and architecture teams to deliver cutting-edge telecom hardware.

Qualifications

• Several years of RTL design in complex ASIC/IP environments.
• Expert SystemVerilog/Verilog skills for high-performance hardware.
• End-to-end ASIC flow: coding, linting, CDC, synthesis, timing.

Responsibilities

• Own major IP blocks from concept to silicon.
• Transform architectural vision into RTL (SystemVerilog/Verilog).
• Lead verification, backend/PD, and architecture teams.
• Balance power, area, and throughput while innovating.

Skills

RTL design

SystemVerilog/Verilog

ASIC flow mastery

DSP/FEC knowledge

Architectural thinking

Job description

Ericsson’s Accelerator IP team in Austin, TX is seeking a Senior RTL Design Engineer to own the microarchitecture of next-generation L1 accelerators from concept to silicon, translating DSP/FEC algorithms into high-performance SystemVerilog.

You will lead major IP blocks end-to-end, drive power/area/throughput trade-offs, and collaborate across verification, backend, and architecture teams to deliver cutting-edge telecom hardware.