Senior RTL Design Engineer - AI Accelerator ASIC

SambaNova; Austin (TX); On-site; USD 120,000 - 200,000; Full time

Benefits offered by this job

Health insurance

Dental insurance

Vision insurance

Disability insurance

Life insurance

AD&D insurance

HSA contributions

FSA options

Headspace access

Gympass+

One Medical

Counseling services (EAP)

EAP access

Job summary

SambaNova Systems is seeking an experienced RTL Design Engineer to own blocks within an RDU ASIC subsystem. You will contribute to microarchitecture, write and debug SystemVerilog, and guide blocks through implementation, tape-out, and silicon bring-up in collaboration with verification and physical design teams.

The role requires strong SystemVerilog skills, a solid digital logic foundation, and experience with power, performance, and area trade-offs on high-speed ASICs.

Qualifications

• BS in EE, CE, or CS required.
• 5+ years of ASIC RTL design experience.
• Strong digital logic and computer architecture knowledge.
• SystemVerilog for high-speed ASICs with power/performance/area trade-offs.
• Experience with AXI, PCIe, Ethernet, and HBM or DDR.
• Proficient with RTL Synthesis, Lint, CDC, and STA workflows.

Responsibilities

• Own blocks within a larger RTL subsystem and contribute to microarchitecture specs.
• Write and debug RTL and carry blocks through implementation and tape-out.
• Collaborate with design verification, physical design, and architecture teams.
• Participate in silicon bring-up and performance tuning.

Skills

ASIC RTL design

SystemVerilog

Power/Performance/Area trade-offs

Computer architecture

Digital logic design

Interconnect protocols

Linting & CDC

SystemVerilog Assertions

Hardware performance analysis

Git

Python & Linux shell

Education

B.S. in Electrical Engineering / Computer Engineering / Computer Science

MS or PhD in EE/CE/CS

Tools

Synthesis tools

Static timing analysis tools

RTL simulators

Linting tools

Job description

SambaNova Systems is seeking an experienced RTL Design Engineer to own blocks within an RDU ASIC subsystem. You will contribute to microarchitecture, write and debug SystemVerilog, and guide blocks through implementation, tape-out, and silicon bring-up in collaboration with verification and physical design teams.

The role requires strong SystemVerilog skills, a solid digital logic foundation, and experience with power, performance, and area trade-offs on high-speed ASICs.