Senior RTL Design Engineer

Oho Group; San Francisco (CA); On-site; USD 140,000 - 190,000; Full time

Job summary

Are you an RTL Design Engineer looking to take the jump to a hugely-growing AI startup revolutionising accelerator technology? This could be the role for you!

We are seeking an RTL Design Engineer to join a fast-growing AI startup focused on accelerator technology. This role involves turning architectural concepts into robust RTL for ASIC/SoC implementations and bringing up silicon.

Qualifications

• Experience in ASIC/SoC design required.
• Strong knowledge of AMBA protocols.
• Experience with high bandwidth memory, HBM/DDR.
• Experience in compute engines for GPU/NPUs is a plus.

Responsibilities

• Design and implement RTL for advanced digital and SoC designs.
• Translate architectural requirements into efficient hardware solutions.
• Optimize designs for performance, power, and area.
• Collaborate with verification and implementation teams to deliver silicon.
• Debug and resolve design issues during development and silicon bring-up.
• Contribute to technical reviews and cross-functional engineering discussions.

Skills

ASIC and SoC design

AMBA protocols

HBM and DDR knowledge

GPU/NPU compute engine design

Job description

Are you an RTL Design Engineer looking to take the jump to a hugely-growing AI startup revolutionising accelerator technology? This could be the role for you!

What you'll be doing

• Design and implement RTL for advanced digital and SoC designs.
• Translate architectural requirements into efficient hardware solutions.
• Optimise designs for performance, power, and area.
• Work with verification and implementation teams to deliver high-quality silicon.
• Debug and resolve design issues throughout development and silicon bring-up.
• Contribute to technical reviews and cross-functional engineering discussions.

What you need

• Strong ASIC and SoC design experience
• Deep understanding of AMBA protocols
• Knowledge of high-bandwidth memory systems (HBM, DDR).
• Experience designing high-performance compute engines in GPU or NPU is a plus.
• Familiarity with chiplet architectures or advanced packaging.
• Experience with performance modeling and architecture exploration.