Senior RTL Design Engineer - AI Compute Platforms

Mueon Corporation; Portland (OR); On-site; USD 110,000 - 165,000; Full time

Job summary

Mueon is seeking an RTL Design Engineer to translate architectures into high-performance, low-power RTL for AI-ready SoCs. You will design synthesizable Verilog/SystemVerilog, collaborate with architecture, verification, and physical design, and drive silicon-ready IP from concept to tape-out.

Responsibilities include RTL development, debugging, simulation, CDC/RDC analysis, linting, and test integration. A strong background in ASIC/FPGA design, Verilog/SystemVerilog, and scripting is required

Qualifications

• Bachelor’s degree or higher in a relevant engineering field.
• Strong RTL development experience for ASIC/FPGA designs.
• Experience with Verilog/SystemVerilog and sim tools.

Responsibilities

• Design and develop synthesizable RTL using Verilog and SystemVerilog for complex digital IP blocks and SoC subsystems
• Translate architectural and microarchitecture specifications into high-perf hardware implementations
• Collaborate with verification engineers to develop verification plans and resolve design issues
• Perform module- and block-level simulation, debugging, and functional validation
• Drive RTL quality through lint, CDC, and RDC analysis and resolution
• Partner with synthesis and physical design teams to optimize timing, power, area

Skills

Digital design fundamentals

Debugging

Collaboration across teams

Analytical skills

Communication

Python scripting

Education

B.S. or M.S. in Electrical Engineering, Computer Engineering, Computer Science

Tools

Verilog/SystemVerilog

Synopsys VCS

Cadence Xcelium

Questa

Job description

Mueon is seeking an RTL Design Engineer to translate architectures into high-performance, low-power RTL for AI-ready SoCs. You will design synthesizable Verilog/SystemVerilog, collaborate with architecture, verification, and physical design, and drive silicon-ready IP from concept to tape-out.

Responsibilities include RTL development, debugging, simulation, CDC/RDC analysis, linting, and test integration. A strong background in ASIC/FPGA design, Verilog/SystemVerilog, and scripting is required