ASIC RTL Design Engineer for AI Inference SoCs

Positron Corporation; United States; Remote; USD 150,000 - 200,000; Full time

Job summary

Positron AI seeks an ASIC Design Engineer to design and deliver IP blocks for inference ASICs/SoCs. You will write and verify SystemVerilog RTL, own select blocks, and follow front-end flows from microarchitecture to RTL signoff.

You will collaborate with architecture, verification and physical design teams, gaining hands-on silicon experience and evolving toward technical ownership while adhering to coding guidelines and signoff checklists.

Qualifications

• BS/MS in EE/CE with 0–3 years of ASIC/SoC RTL design experience (internships and relevant graduate research count).
• Solid working knowledge of SystemVerilog/Verilog for synthesizable RTL design.
• Understanding of digital design fundamentals: clocking, resets, pipelining, FSMs, FIFOs, and clock domain crossing.
• Exposure to front-end tools and flows (simulation, lint, synthesis, or STA).
• Familiarity with at least one of AMBA AXI/AHB/APB, DDR/HBM, PCIe, cache/memory hierarchies, or datapath design.
• Scripting ability in Python, Tcl, or similar.
• Strong problem-solving skills, eagerness to learn, and clear written and verbal communication.

Responsibilities

• Implement clean, parameterized SystemVerilog RTL for assigned blocks based on microarchitecture specs.
• Contribute to microarchitecture documentation and define block interfaces.
• Add embedded assertions and follow guidelines for clocking, resets, and power intent.
• Run lint, CDC/RDC, and synthesis checks and resolve issues with team support.
• Assist timing analysis and work with PD on block-level timing fixes.
• Track and report PPA metrics and propose optimizations.
• Support integration of standard interfaces and IP (e.g., AMBA AXI, DMA engines, memory controllers).
• Learn protocol requirements for high-performance interconnects and memory interfaces.
• Follow coding guidelines, IP packaging standards, and signoff checklists.
• Write and maintain scripts (Python/Tcl/Make) to improve design flows and productivity.
• Collaborate with Verification to review test plans and close coverage on blocks.
• Assist bring-up and post-silicon debug activities as needed.
• Participate in design reviews and mentorship from senior engineers.

Skills

SystemVerilog/Verilog

Digital design fundamentals

Front-end tools experience

Python scripting

Tcl scripting

AMBA AXI/AXI variant familiarity

Problem-solving

Education

BS/MS in EE/CE

Job description

Positron AI seeks an ASIC Design Engineer to design and deliver IP blocks for inference ASICs/SoCs. You will write and verify SystemVerilog RTL, own select blocks, and follow front-end flows from microarchitecture to RTL signoff.

You will collaborate with architecture, verification and physical design teams, gaining hands-on silicon experience and evolving toward technical ownership while adhering to coding guidelines and signoff checklists.