RTL Design Engineer — AI Chip Microarchitecture & Tapeout

Normal Computing Corp.; Mountain View (CA); On-site; USD 140,000 - 210,000; Full time

Job summary

Normal Computing is an applied AI company building foundational hardware and software for the semiconductor industry, with a global presence including Mountain View, CA. We are seeking an RTL Design Engineer to own RTL from microarchitecture to tapeout, collaborating across architecture, verification, and physical design to deliver high-performance digital logic.

You will craft synthesizable SystemVerilog, work with verification to close coverage, and coordinate with physical design for timing,

Qualifications

• Hands-on experience writing production RTL in SystemVerilog and closing it through synthesis and place-and-route.
• Experience in closing coverage to a high level.
• At least one tapeout in your background, from any node and any company size.
• Experience working on datapaths, pipelines, or custom logic where the microarchitecture was not fully specified upfront.
• Strong debugging instincts across simulation, waveforms, and formal counterexamples.
• Ability to work directly with architects and physical designers without needing a large intermediary layer.
• Industry experience in ASIC or SoC design.

Responsibilities

• Write and own synthesizable RTL in SystemVerilog across blocks ranging from datapath logic to control and memory interfaces.
• Translate high-level specifications into implementable microarchitectures with architecture input.
• Review verification plans and assist on debug to close coverage.
• Collaborate with physical design on timing closure, floorplanning constraints, and DFT.
• Participate in design reviews and contribute to architecture decisions beyond implementation.
• Support tapeout preparation, integration, and post-silicon bring-up as needed.

Skills

RTL Design

SystemVerilog

ASIC/SoC design

Debugging

Tapeout

Microarchitecture

Job description

Normal Computing is an applied AI company building foundational hardware and software for the semiconductor industry, with a global presence including Mountain View, CA. We are seeking an RTL Design Engineer to own RTL from microarchitecture to tapeout, collaborating across architecture, verification, and physical design to deliver high-performance digital logic.

You will craft synthesizable SystemVerilog, work with verification to close coverage, and coordinate with physical design for timing,