Senior RTL Design Engineer for LLM Inference ASIC

Acceler8 Talent; California; On-site; USD 170,000 - 230,000; Full time

Job summary

Acceler8 Talent is seeking an RTL Design Engineer in Palo Alto to help build a next-generation AI accelerator. You will own RTL across ASIC/SoC blocks, driving from architectural concepts through implementation, verification, and tapeout readiness.

The role demands hands-on design leadership, strong Verilog/SystemVerilog expertise, and close collaboration with verification and physical design teams to meet timing, power and area targets.

Qualifications

• Extensive digital hardware design experience with hands-on ASIC/SoC RTL ownership.
• Strong proficiency in Verilog and SystemVerilog.
• Proven ability to derive RTL from architectural specs and implement it.
• Deep microarchitecture knowledge: datapaths, state machines, control logic.
• Knowledge of PPA optimization and its impact on implementation.
• Experience debugging complex RTL and timing issues with teams.
• History collaborating with verification, architecture, and physical teams.
• Staff-to-Principal level judgment with hands-on RTL design focus.

Responsibilities

• Translate architectures into detailed microarchitecture and synthesizable RTL.
• Design and optimize datapaths, control logic, and interfaces.
• Trade off throughput, latency, power, and timing in designs.
• Own RTL development, debugging, and integration for major blocks.
• Collaborate with verification to define functionality and debug issues.
• Coordinate with physical design to analyse synthesis and timing feedback.
• Drive design improvements based on timing, power, and area needs.
• Own blocks through integration, verification closure, and tapeout readiness.
• Document key design decisions, risks, and trade-offs.

Skills

Verilog/SystemVerilog

RTL development

PPA optimization

RTL debugging

Cross-team collaboration

Hands-on design

Tools

Synthesis

Static Timing Analysis

Physical design feedback

Job description

Acceler8 Talent is seeking an RTL Design Engineer in Palo Alto to help build a next-generation AI accelerator. You will own RTL across ASIC/SoC blocks, driving from architectural concepts through implementation, verification, and tapeout readiness.

The role demands hands-on design leadership, strong Verilog/SystemVerilog expertise, and close collaboration with verification and physical design teams to meet timing, power and area targets.