Senior RTL Subsystem Architect – SoC Design

Synopsys, Inc.; Sunnyvale (CA); On-site; USD 180,000 - 260,000; Full time

Job summary

Synopsys, Inc. is seeking an experienced RTL design leader to drive complex ASIC digital subsystems from concept to silicon. You will define architecture, translate requirements into clear specifications, and deliver high-quality RTL that is robust and scalable.

You will work across design, verification, DFT and implementation, with experience in UCIe, Ethernet, UALink, and AMBA. Mentoring junior engineers and leading design reviews are also key responsibilities.

Qualifications

• 8+ years of RTL design and subsystem architecture for ASIC/SoC projects.
• Expertise in Verilog/SystemVerilog with linting, CDC, RDC, and formal verification.
• Experience with UCIe, Ethernet, UALink, and AMBA protocols.
• Strong leadership, cross-functional collaboration, and design-review experience.
• Knowledge of low power design methodologies and DFT architectures.

Responsibilities

• Lead the subsystem lifecycle from requirements and architecture through release.
• Develop subsystem architecture, specs, and high-quality RTL micro-architecture.
• Drive design quality via RTL linting, CDC, RDC, and close collaboration with verification, DFT, and implementation teams.
• Integrate UCIe, Ethernet, UALink, and AMBA protocols into subsystem designs.
• Mentor junior engineers and participate in technical reviews and design excellence.

Skills

RTL design

Subsystem architecture

Verilog/SystemVerilog

RTL linting

CDC/RDC

DFT

Cross-functional leadership

Mentoring

UCIe/AMBA protocols

Ethernet/UCIe

Education

BSEE/BSCE/MSEE/MSCE or higher

Tools

EDA tools

Formal verification tools

Job description

Synopsys, Inc. is seeking an experienced RTL design leader to drive complex ASIC digital subsystems from concept to silicon. You will define architecture, translate requirements into clear specifications, and deliver high-quality RTL that is robust and scalable.

You will work across design, verification, DFT and implementation, with experience in UCIe, Ethernet, UALink, and AMBA. Mentoring junior engineers and leading design reviews are also key responsibilities.