RTL Lead Engineer

Mirafra Technologies; Santa Clara (CA); On-site; USD 160,000 - 230,000; Full time

Job summary

Mirafra Technologies in Santa Clara, CA is seeking a senior RTL engineer to translate system requirements into robust microarchitectures and drive HW/SW co-design across AI workloads and memory systems.

You will collaborate with software teams to define programming models, interfaces, and data movement, while leading RTL implementations and architecture reviews to meet performance and power targets.

Qualifications

• Strong RTL design experience in complex SoCs, CPUs, GPUs, AI accelerators or related systems.
• Deep understanding of digital design fundamentals and microarchitecture.
• Experience with Verilog/SystemVerilog and modern RTL development methodologies.
• Familiarity with memory systems, interconnect fabrics, cache hierarchies, and system-level data movement.

Responsibilities

• Collaborate with architects to translate system requirements into robust microarchitectures.
• Drive hardware/software co-design across AI workloads, memory systems, runtime software, and system architecture.
• Partner with software teams to define programming models, execution flows, memory hierarchies, and performance-critical interfaces.
• Drive design decisions across compute engines, memory subsystems, interconnect, control logic, and system infrastructure.
• Develop high-quality, power-efficient, and scalable RTL implementations.
• Conduct architecture and RTL reviews to ensure performance, power, and area goals are achieved.
• Mentor and develop other RTL engineers.

Skills

RTL design

SystemVerilog

microarchitecture

hardware/software co-design

Performance/power optimization

Education

Bachelor's degree in Electrical Engineering or related field

Job description

• Collaborate with architects to translate system requirements into robust microarchitectures.
• Drive hardware/software co-design across AI workloads, memory systems, runtime software, and system architecture.
• Partner closely with software teams to define programming models, execution flows, memory hierarchies, and performance-critical interfaces.
• Drive design decisions across compute engines, memory subsystems, interconnect, control logic, and system infrastructure.
• Develop high-quality, power-efficient, and scalable RTL implementations.
• Conduct architecture and RTL reviews to ensure performance, power, and area goals are achieved.
• Work closely with performance modelling, verification, physical design, and software teams throughout the development cycle.
• Help establish engineering processes and design methodologies as the organization grows.
• Mentor and develop other RTL engineers.

Required Qualifications

• Strong RTL design experience in complex SoCs, CPUs, GPUs, AI accelerators, networking devices, or related systems.
• Deep understanding of digital design fundamentals and microarchitecture.
• Experience with Verilog/SystemVerilog and modern RTL development methodologies.
• Familiarity with memory systems, interconnect fabrics, cache hierarchies, and system-level data movement.
• Experience balancing performance, power, area, and design complexity.
• Proven ability to drive complex technical projects from concept through silicon bring-up.
• Experience with hardware/software co-design and performance optimization across the full system stack.
• Familiarity with AI runtimes, operating systems, firmware, drivers, or other system software layers is highly desirable.

Preferred Qualifications

• Experience with AI accelerators, machine learning hardware, or edge AI platforms.
• Experience with robotics, autonomous systems, automotive, aerospace, or other real-time computing environments.
• Knowledge of low-power design techniques and power management architectures.