Senior RTL Design Engineer - ASIC/SoC Expert

Programmers; United States; Presencial; USD 120.000 - 180.000; Jornada completa

Descripción de la vacante

Programmers in the United States seeks an experienced ASIC/SoC design engineer to lead RTL design and tape-outs in deep sub-micron technology. You will own Verilog/SystemVerilog design, manage the RTL-to-PD flow, and collaborate with cross-functional teams on high-performance, low-latency data paths.

Applicants should have a track record of successful tape-outs, expertise with AXI interfaces, and a deep understanding of physical design tradeoffs among performance, area, and power.

Formación

• 9+ years of related engineering experience or equivalent degree combination.
• 8+ years delivering IP/ASIC/SoC designs for arbitration and fabric logics.
• 8+ years Digital Design with RTL coding in Verilog/SystemVerilog; RTL2PD flow experience.

Conocimientos

Verilog/SystemVerilog RTL coding

RTL2PD flow setup

Lint/CDC/RDC/FEV debugging

Timing constraints

Synthesis

Educación

Bachelor's in EE/CE/CS

Master's in EE/CE/CS

Doctorate in EE/CE/CS

Herramientas

AXI interfaces

RTL2PD tools

Synthesis tools

Descripción del empleo

Programmers in the United States seeks an experienced ASIC/SoC design engineer to lead RTL design and tape-outs in deep sub-micron technology. You will own Verilog/SystemVerilog design, manage the RTL-to-PD flow, and collaborate with cross-functional teams on high-performance, low-latency data paths.

Applicants should have a track record of successful tape-outs, expertise with AXI interfaces, and a deep understanding of physical design tradeoffs among performance, area, and power.