Senior RTL/ASIC Design Engineer — High-Performance SoC

SpaceX; Palo Alto (CA); On-site; USD 175,000 - 280,000; Full time

Benefits offered by this job

Stock options

Long-term incentives

Discretionary bonuses

Employee stock purchase plan

Medical, vision, dental coverage

401(k) retirement plan

Paid parental leave

Paid vacation & holidays

Job summary

SpaceX is hiring a Senior RTL Design Engineer (Silicon Engineering) to develop next‑generation ASICs for Starlink. You will define micro‑architecture, implement RTL in Verilog/SystemVerilog, and drive synthesis, verification, and timing closure with a cross‑functional team.

Requirements include 5+ years in RTL implementation, experience with clock domain crossings, embedded subsystems, AXI/AHB, and HDL tools.

Qualifications

• 5+ years of RTL implementation experience.

Responsibilities

• Evaluate architectural trade-offs based on features, performance requirements and system limitations.
• Define micro-architecture, implement the RTL in Verilog/SystemVerilog, integrate that in top level and deliver the fully verified, synthesis/timing clean design.
• Work closely with verification team to ensure all aspects of the design are covered and verified.
• Provide timing constraint for those IPs and support the physical implementation team (synthesis, timing closure, formality check).
• Participate in silicon bring-up and validation.

Skills

RTL implementation

Verilog/SystemVerilog

Clock domain crossings

ASIC/SoC integration

Embedded CPU subsystems

AXI/AHB protocols

High speed design

Python scripting

EDA tools

Education

Bachelor’s degree in electrical engineering, computer engineering, or computer science

Tools

HDL simulators

EDA tools

HDL Lint tools

Job description

SpaceX is hiring a Senior RTL Design Engineer (Silicon Engineering) to develop next‑generation ASICs for Starlink. You will define micro‑architecture, implement RTL in Verilog/SystemVerilog, and drive synthesis, verification, and timing closure with a cross‑functional team.

Requirements include 5+ years in RTL implementation, experience with clock domain crossings, embedded subsystems, AXI/AHB, and HDL tools.