Senior RTL/ASIC Design Engineer - High-Performance Chips

Starlink; Redmond (WA); On-site; USD 165,000 - 270,000; Full time

Benefits offered by this job

Stock options

Medical, vision & dental

Job summary

SpaceX is seeking a Sr. RTL Design Engineer (Silicon Engineering) to develop cutting-edge ASICs for Starlink hardware in Redmond, WA.

You will define micro-architecture, implement RTL in Verilog/SystemVerilog, and verify designs end-to-end, collaborating with verification, software, and physical design teams. You will evaluate architectural trade-offs, support timing closure, and participate in silicon bring-up, with a focus on high-performance, power-efficient designs for space-grade systems.

Qualifications

• Bachelors degree in electrical/computer engineering or computer science.
• 5+ years of RTL implementation experience.
• Strong problem-solving and collaboration skills.

Responsibilities

• Evaluate architectural trade-offs based on features, performance requirements and system limitations.
• Define micro-architecture, implement the RTL in Verilog/SystemVerilog, integrate that in top level and deliver the fully verified, synthesis/timing clean design.
• Work closely with verification team to ensure all aspects of the design are covered and verified.
• Provide timing constraint for those IPs and support the physical implementation team (synthesis, timing closure, formality check).
• Participate in silicon bring-up and validation.

Skills

RTL implementation

Clock domain crossings

Team collaboration

Problem solving

Education

Bachelor’s degree in electrical engineering, computer engineering, or computer science

Tools

Verilog/SystemVerilog

HDL simulators

HDL Lint tools

EDA tools

Python scripting

Job description

SpaceX is seeking a Sr. RTL Design Engineer (Silicon Engineering) to develop cutting-edge ASICs for Starlink hardware in Redmond, WA.

You will define micro-architecture, implement RTL in Verilog/SystemVerilog, and verify designs end-to-end, collaborating with verification, software, and physical design teams. You will evaluate architectural trade-offs, support timing closure, and participate in silicon bring-up, with a focus on high-performance, power-efficient designs for space-grade systems.