FPGA/ASIC Design Engineer — High-Impact Silicon

Starlink; Irvine (CA); On-site; USD 125,000 - 195,000; Full time

Benefits offered by this job

Stock options

401(k) plan

Health, vision & dental coverage

Paid parental leave

3 weeks paid vacation

10+ paid holidays

Employee Stock Purchase Plan

Job summary

SpaceX is seeking a motivated FPGA/ASIC Design Engineer (Silicon Engineering) in Irvine to design SoC blocks for Starlink. You will work across teams from architecture to validation on space and ground systems, delivering high‑reliability FPGA/ASIC solutions.

Qualifications include a Bachelor’s in EE/CE/CS/Physics and 1+ years RTL design with SystemVerilog/Verilog/VHDL, plus experience with HDL tools and DSP datapaths. This is a full‑time, on‑site role with strong benefits and ITAR compliance.

Qualifications

• Bachelor’s degree in a relevant engineering or physics field.
• 1+ years of RTL design experience using SystemVerilog/Verilog/VHDL.
• Strong fundamentals in digital design and signal processing.

Responsibilities

• Design ASICs and/or FPGAs for Starlink projects, implementing complex SoC blocks and SoC integration tasks using Verilog/SystemVerilog.
• Optimize designs for power, performance and area.
• Participate in full ASIC/FPGA design lifecycle from architecture to validation.
• Build tools to analyze data collected on orbit and in the lab.
• Engage in high-level architectural design for test systems and integration with DSP subsystems.
• Collaborate with software engineers to develop production software for your designs.

Skills

SystemVerilog

Verilog

VHDL

Python

C/C++

DSP design

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or Physics

Master’s in Electrical/Computer Engineering or related field

Tools

HDL simulators (VCS, Questa, IES)

Vivado

Quartus II

Spyglass

AXI/APB protocols

Job description

SpaceX is seeking a motivated FPGA/ASIC Design Engineer (Silicon Engineering) in Irvine to design SoC blocks for Starlink. You will work across teams from architecture to validation on space and ground systems, delivering high‑reliability FPGA/ASIC solutions.

Qualifications include a Bachelor’s in EE/CE/CS/Physics and 1+ years RTL design with SystemVerilog/Verilog/VHDL, plus experience with HDL tools and DSP datapaths. This is a full‑time, on‑site role with strong benefits and ITAR compliance.