Senior ASIC Verification Engineer - Digital RTL

SpaceX; Austin (TX); On-site; USD 180,000 - 240,000; Full time

Job summary

SpaceX seeks a Sr. ASIC Design Verification Engineer to join the Silicon Engineering team. You will verify digital ASIC designs at block and system levels, write test plans, and develop test benches to ensure robust functionality of Starlink hardware.

Join a world‑class, cross‑functional group delivering next‑generation chips for space and ground infrastructures. Top candidates will have 5+ years in verification, strong coding skills (Python), and experience with UVM/OVM/VMM methodologies in a

Qualifications

• Bachelor’s degree in electrical engineering or computer engineering.
• 5+ years of experience with design verification and test bench development.
• Experience with verification methodologies such as UVM/OVM/VMM.
• Strong problem-solving and coding skills.
• RTL design, chip bring‑up and post‑silicon validation experience.

Responsibilities

• Responsible for digital ASIC verification at block and system level.
• Write and review test plans, develop test harnesses and test sequences.
• Responsible for test plan execution, running regressions, code and functional coverage closure.
• Contribute towards pre‑silicon verification, chip bring‑up and post‑silicon validation.
• Be a hands‑on self‑starter who can execute the steps required to fully verify a complex digital designs.

Skills

Design verification

Test bench development

Object-oriented programming

Python scripting

RTL design

Chip bring-up

Education

Bachelor’s degree in electrical engineering or computer engineering

Advanced degree in electrical engineering or computer engineering

Tools

UVM/OVM/VMM

Job description

SpaceX seeks a Sr. ASIC Design Verification Engineer to join the Silicon Engineering team. You will verify digital ASIC designs at block and system levels, write test plans, and develop test benches to ensure robust functionality of Starlink hardware.

Join a world‑class, cross‑functional group delivering next‑generation chips for space and ground infrastructures. Top candidates will have 5+ years in verification, strong coding skills (Python), and experience with UVM/OVM/VMM methodologies in a