Turn this role into an interview — a resume and cover letter built around what this employer wants.
SpaceX is seeking a Sr. RTL Design Engineer (Silicon Engineering) to develop next-generation ASICs for Starlink ground and space infrastructure. You will design, implement, verify RTL in Verilog/SystemVerilog, and work with cross-disciplinary teams to push performance and power.
The role requires strong problem solving for clock domains, AXI/AMBA interfaces, and high-speed, low-power design techniques. Applicants should have a B.S. in ECE/CS and 5+ years RTL experience; ITAR compliance applies.
SpaceX is seeking a Sr. RTL Design Engineer (Silicon Engineering) to develop next-generation ASICs for Starlink ground and space infrastructure. You will design, implement, verify RTL in Verilog/SystemVerilog, and work with cross-disciplinary teams to push performance and power.
The role requires strong problem solving for clock domains, AXI/AMBA interfaces, and high-speed, low-power design techniques. Applicants should have a B.S. in ECE/CS and 5+ years RTL experience; ITAR compliance applies.