Senior ASIC RTL Design Engineer — Space-Grade SoCs

Starlink; Irvine (CA); On-site; USD 165,000 - 265,000; Full time

Job summary

SpaceX is seeking a Sr. RTL Design Engineer (Silicon Engineering) to develop next‑generation ASICs for Starlink and space-grade systems. You will work with cross‑disciplinary teams to design, verify, and bring up silicon that powers global connectivity.

The role requires advanced RTL skills, SystemVerilog/Verilog experience, and collaboration with verification and physical teams to meet mission deadlines and performance goals.

Qualifications

• Bachelors degree in electrical engineering, computer engineering, or computer science.
• 5+ years of experience in RTL implementation.

Responsibilities

• Evaluate architectural trade-offs based on features, performance requirements and system limitations.
• Define micro-architecture, implement the RTL in Verilog/SystemVerilog, integrate that in top level and deliver the fully verified, synthesis/timing clean design.
• Work closely with verification team to ensure all aspects of the design are covered and verified.
• Provide timing constraint for those IPs and support the physical implementation team (synthesis, timing closure, formality check).
• Participate in silicon bring‑up and validation.

Skills

RTL Design

SystemVerilog

Verilog

ASIC/SoC integration

Scripting (Python)

Education

Bachelor’s degree in Electrical/Computer Engineering or Computer Science

Tools

HDL simulators

HDL Lint tools

Job description

SpaceX is seeking a Sr. RTL Design Engineer (Silicon Engineering) to develop next‑generation ASICs for Starlink and space-grade systems. You will work with cross‑disciplinary teams to design, verify, and bring up silicon that powers global connectivity.

The role requires advanced RTL skills, SystemVerilog/Verilog experience, and collaboration with verification and physical teams to meet mission deadlines and performance goals.