Senior Principal SI/PI Engineer - High-Speed SerDes

Cadence Design Systems; San Jose (CA); Hybrid; USD 154,000 - 286,000; Full time

Benefits offered by this job

401(k) match

Employee stock purchase plan

Medical/Dental/Vision coverage

Job summary

Cadence Design Systems is hiring a Sr Principal SI/PI Engineer to join the HPP IP R&D Group. You will lead hands-on SI/PI design, testing, and model extraction for high-speed IP products, working closely with chip designers and customers to optimize performance.

The role requires a strong background in SerDes, PCB/FCBGA design, and IBIS-AMI simulations, with excellent communication skills to interact with internal teams and external customers.

Qualifications

• MS or Ph.D. in Electrical Engineering (or similar).
• 3+ years of experience with high speed SerDes and PHYs.
• Strong understanding of high speed SerDes architecture.
• Hands-on lab experience with high speed instruments (oscilloscopes, TDRs, VNAs, spectrum analyzers).
• Experience with 3D/2.5D extraction tools like Sigrity Clarity/PowerSI or Ansys HFSS/SIwave.
• Experience with IBIS-AMI model simulations.
• Experience with lab measurement correlation to simulations.
• Good understanding of PCB and FCBGA design rules.

Responsibilities

• Work on test chip package SI/PI optimization and verification.
• Develop evaluation board design optimization for SI/PI performance.
• Provide extracted and measured channel models for chip designers.
• Help with package and PCB SI/PI design guidelines and customer support.
• Review customer package and board designs and simulation results.
• Provide feedback to customers to optimize IP performance.
• Perform link simulations using S-parameter models and IBIS-AMI models.
• Assist with SI/PI debugging for test chips or customer ASICs.

Skills

SerDes architecture

Debugging

Communication

Lab problem solving

Education

MS in Electrical Engineering

PhD in Electrical Engineering

Tools

IBIS-AMI

Sigrity Clarity

PowerSI

Ansys HFSS

SIwave

Oscilloscopes

TDRs

VNAs

Spectrum Analyzers

Job description

Cadence Design Systems is hiring a Sr Principal SI/PI Engineer to join the HPP IP R&D Group. You will lead hands-on SI/PI design, testing, and model extraction for high-speed IP products, working closely with chip designers and customers to optimize performance.

The role requires a strong background in SerDes, PCB/FCBGA design, and IBIS-AMI simulations, with excellent communication skills to interact with internal teams and external customers.