Senior SI/PI Engineer for High-Speed AI Hardware

Socket.dev; Los Altos (CA); On-site; USD 150,000 - 190,000; Full time

Job summary

Majestic Labs is seeking a Senior Signal Integrity (SI) and Power Integrity (PI) Engineer to own end-to-end electrical link performance for high-speed interconnects—from architecture and pre-silicon modeling through silicon bring-up and high-volume manufacturing.

You will drive SI/PI closure for SerDes, PCIe Gen5/Gen6, and memory interfaces, building 3D/2.5D models and correlating with lab measurements (VNA, TDR, BERT, scope) to validate performance.

Qualifications

• 10+ years of hands-on SI/PI engineering experience across product lifecycle.
• Experience from architecture to production and high-volume manufacturing.
• Deep knowledge of high-speed SerDes signaling and PCIe link architecture.
• Proficiency with parallel/source-synchronous interfaces (DDR/memory buses).
• Proficiency with COM-based analysis and IBIS-AMI modeling for margin assessments.
• Experience with HFSS, PowerSI, ADS, MATLAB tooling for analysis and automation.
• Hands-on SI/PI lab testing with VNA, TDR, TDT, and oscilloscopes.
• Understanding of PDN analysis and co-design across chip/package/board.
• Strong communication to present risks and trade-offs to stakeholders.
• Scripting in Python for flow automation or data analysis.

Responsibilities

• Own SI/PI analysis for end-to-end high-speed links including package, PCB, and interconnects.
• Drive SI/PI closure for SerDes interfaces (112G/224G-class) and PCIe Gen5/Gen6+.
• Perform pre-silicon modeling, budgeting, and margin analysis using eye methods.
• Build 3D/2.5D EM models and validate against lab measurements (VNA, TDR, BERT).
• Conduct PDN analysis and decoupling strategy across chip, package, and board.
• Use ADS and MATLAB for circuit-level simulation and automation of data workflows.
• Support silicon bring-up, debugging, and field issue resolution with data-driven actions.
• Collaborate with ASIC, package, PCB, and mechanical teams to set design rules.
• Lead products through DVT/PVT and high-volume manufacturing with test data correlation.
• Contribute to internal methodology, tooling, and design guidelines.

Skills

SI/PI engineering

High-speed SerDes

PCIe Gen5/Gen6

DDR/Memory interfaces

Channel modeling

Lab measurement

Cross-functional collaboration

Announcing trade-offs

Troubleshooting

Scripting (Python)

Tools

Ansys HFSS

Ansys PowerSI

Keysight ADS

MATLAB

Job description

Majestic Labs is seeking a Senior Signal Integrity (SI) and Power Integrity (PI) Engineer to own end-to-end electrical link performance for high-speed interconnects—from architecture and pre-silicon modeling through silicon bring-up and high-volume manufacturing.

You will drive SI/PI closure for SerDes, PCIe Gen5/Gen6, and memory interfaces, building 3D/2.5D models and correlating with lab measurements (VNA, TDR, BERT, scope) to validate performance.