Senior SIPI Design Engineer: High-Speed SerDes & PDN

Microchip; San Jose (CA); On-site; USD 91,000 - 232,000; Full time

Benefits offered by this job

Health benefits day one

ESPP with 2-year look back

Job summary

Microchip Technology Inc. in San Jose, CA is seeking a Senior Technical Staff Engineer - Design (Signal & Power Integrity) to lead SIPI methodologies for high-speed FPGA products, collaborating with global teams to deliver system-level solutions across die, package, and boards.

The ideal candidate has 15+ years in SIPI, a BS in EE, strong PDN, SerDes, and channel modeling experience, and proficiency with HFSS, Siwave, HSPICE, and ADS.

Qualifications

• BS in Electrical Engineering or Electronics required.
• 15+ years of relevant experience in SIPI and high-speed design.
• 10+ years hands-on SIPI experience across Die, Package, and Boards.
• Strong PCB design/layout understanding and PDN optimization.
• Experience with SerDes, eye diagrams, jitter, and channel modeling.

Responsibilities

• Develop and drive SIPI methodologies for high-speed FPGA products.
• Collaborate with global teams to deliver system-level SIPI solutions.
• Perform pre-layout and post-layout SIPI simulations.
• Guide die changes based on simulation results and optimize PDN.
• Mentor SIPI engineers and advance design methodologies.

Skills

SIPI expertise

Signal Integrity

Power Integrity

Analytical skills

Communication skills

Education

BS in Electrical Engineering

MS degree preferred

Tools

HFSS

Siwave

HyperLynx

HSPICE

Keysight ADS

Job description

Microchip Technology Inc. in San Jose, CA is seeking a Senior Technical Staff Engineer - Design (Signal & Power Integrity) to lead SIPI methodologies for high-speed FPGA products, collaborating with global teams to deliver system-level solutions across die, package, and boards.

The ideal candidate has 15+ years in SIPI, a BS in EE, strong PDN, SerDes, and channel modeling experience, and proficiency with HFSS, Siwave, HSPICE, and ADS.