Senior SI/PI Engineer for High-Speed AI Hardware

Majestic Labs ai; Los Altos (CA); On-site; USD 150,000 - 210,000; Full time

Job summary

Majestic Labs is seeking a Senior SI/PI Engineer to own end-to-end signal and power integrity for high-speed interconnects, from architecture through production. You will tackle SerDes interfaces (224G class), PCIe, and memory links, driving design closure with cross-functional teams.

We expect 10+ years of hands-on experience, strong lab skills with VNA/TDR, and proficiency in modeling tools like HFSS/PowerSI and MATLAB.

Qualifications

• 10+ years hands-on SI/PI engineering experience in hardware industry.
• Experience across the full product lifecycle from architecture to production.
• Deep knowledge of high-speed SerDes interfaces (224G class) and PCIe architecture.
• Strong experience with DDR/ chip-to-chip interconnects.
• Proficiency with IBIS-AMI modeling for channel compliance and margin.
• Hands-on lab testing and measurement with VNA, TDR, and scopes.
• Ability to work with cross-functional teams to drive designs to closure.
• Excellent written and verbal communication skills.

Responsibilities

• Own SI/PI analysis for end-to-end high-speed links including package, connector, PCB, and cable interconnects.
• Drive SI/PI closure for SerDes interfaces (112G/224G-class) and PCIe across generations.
• Perform pre-silicon modeling, budgeting, and margin analysis using channel margin tools.
• Build and correlate 3D/2.5D EM models against lab measurements to validate performance.
• Conduct PDN analysis and decoupling strategy across chip, package, and board.
• Use ADS and MATLAB for circuit simulations and data post-processing.
• Support silicon bring-up, debugging, and field/production issues.
• Collaborate with ASIC, package, PCB, and mechanical teams to define rules and guidelines.
• Lead DVT/PVT and high-volume manufacturing readiness, including test correlation.
• Contribute to internal methodologies and tooling.

Skills

SI/PI engineering

High-speed SerDes (224G+)

PCIe design (Gen5/Gen6+)

PCB/Package interconnects

HFSS/PowerSI

MATLAB/ADS

Lab testing (VNA/TDR)

Cross-functional collaboration

Verbal and written communication

Scripting (Python)

Tools

Ansys HFSS

Ansys PowerSI

Keysight ADS

MATLAB

Job description

Majestic Labs is seeking a Senior SI/PI Engineer to own end-to-end signal and power integrity for high-speed interconnects, from architecture through production. You will tackle SerDes interfaces (224G class), PCIe, and memory links, driving design closure with cross-functional teams.

We expect 10+ years of hands-on experience, strong lab skills with VNA/TDR, and proficiency in modeling tools like HFSS/PowerSI and MATLAB.