Senior SerDes SI/PI Engineer

Ansys, Inc.; Boxborough (MA); On-site; USD 165,000 - 247,000; Full time

Benefits offered by this job

Health benefits

Equity plans

Annual bonus potential

Job summary

Synopsys is hiring a high-speed SerDes SIPI engineer to own end-to-end signoff for PCIe Gen6/7/8, E224G, E448G, and CXL interfaces. You will model, simulate, and correlate across silicon, package, and board while mentoring peers and defining robust design flows.

You will lead lab characterization, perform bench tests, and drive design fixes with data-driven decisions. Strong scripting and communication skills are essential.

Qualifications

• 1–2+ years of relevant experience in high-speed SI/PI for SerDes links (silicon + package + board).
• Strong fundamentals in EM, transmission lines, modeling, and signoff criteria.
• Expertise with high-speed link concepts: insertion/return loss, impedance control, NEXT/FEXT, jitter/noise sources, equalization, BER.
• Experience with lab correlation and measurement techniques (TDR, VNA, eye/jitter) and validation teams.
• Proficiency in scripting/automation for flow enablement (Python preferred).
• Demonstrated technical leadership: mentoring, design reviews, cross-functional influence.

Responsibilities

• Lead end-to-end SIPI for high-speed interfaces (PCIe Gen6/7/8, E224G, E448G, CXL over PCIe) across silicon, interposer, package, PCB, and fixtures.
• Drive channel modeling and correlation across time- and frequency-domain analyses (S-parameters, TDR, crosstalk, jitter budgeting).
• Own SI signoff methodology for SerDes channels, including model extraction and de-embedding.
• Collaborate with circuit/PHY, interposer/package, board, and product teams to diagnose issues and propose fixes with quantified risk/benefit.
• Plan and run bench characterization, compliance testing support, and fixture design guidance; document learnings.
• Define, improve SIPI flows, requirements, and checklists; mentor engineers and lead reviews.
• Provide technical leadership: set priorities, drive cross-project reuse, influence architecture.

Skills

High-speed SI/PI

SerDes

EM theory

SIPI signoff

Modeling & simulation

Lab correlation

Python scripting

Mentoring

Cross-functional collaboration

Education

B.S. in Electrical/Electronic Engineering

MS/PhD preferred

Tools

HSPICE

Keysight ADS/SystemVue

Ansys HFSS

SIwave

AEDT

Cadence Sigrity

MATLAB

Python

Job description

Synopsys is hiring a high-speed SerDes SIPI engineer to own end-to-end signoff for PCIe Gen6/7/8, E224G, E448G, and CXL interfaces. You will model, simulate, and correlate across silicon, package, and board while mentoring peers and defining robust design flows.

You will lead lab characterization, perform bench tests, and drive design fixes with data-driven decisions. Strong scripting and communication skills are essential.