Principal SI/PI Engineer - 18231

Synopsys, Inc.; Boxborough (MA); Hybrid; USD 150,000 - 230,000; Full time

Job summary

Synopsys, Inc. is seeking a senior engineer to lead SIPI for high‑speed SerDes interfaces across silicon, interposer, package, and board. You will own end‑to‑end signoff and mentor teammates.

The role requires deep modeling, measurement, and collaboration with cross‑functional teams; you’ll drive reproducible flows and document learnings.

Qualifications

• Bachelor’s degree in Electrical/Electronic Engineering or related field.
• 12+ years of experience in high-speed SI/PI for SerDes links (silicon + package + board).
• Strong fundamentals in EM, transmission lines, modeling, and analysis.
• Expertise with high-speed links: insertion/return loss, impedance control, NEXT/FEXT, jitter/noise, equalization, BER.

Responsibilities

• Lead end-to-end SIPI for high-speed interfaces (PCIe Gen6/7/8, E224G, E448G, CXL over PCIe).
• Drive channel modeling and correlation across time- and frequency-domain analyses (S-parameters, TDR, crosstalk).
• Own SI signoff methodology for SerDes channels; de-embedding and bandwidth checks.

Skills

high‑speed SI/PI

SIPI for SerDes

EM theory

channel modeling

TD/FD analysis

bench characterization

lab correlation

Python scripting

team mentoring

Education

B.S. in Electrical Engineering

M.S./Ph.D. preferred

Tools

HSPICE

Keysight ADS/System Vue

Ansys HFSS/SIwave/AEDT

Cadence Sigrity

MathWorks SIMULINK

Job description

We are open to hiring in Austin, Hillsboro, and the Bay Area as well.

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars, machine learning to artificial intelligence. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

We develop and deliver industry-leading high-speed interface IP and system solutions, enabling customers to build reliable, high-performance products across advanced nodes and packaging technologies.

You Are:

You are a highly skilled and passionate engineer with a deep understanding of high-speed signal and power integrity, particularly in the realm of SerDes interfaces. With a proven track record in end-to-end SIPI for advanced links such as PCI Express (Gen6/7/8), E224G, E448G, and CXL (over PCIe), you thrive on solving complex engineering challenges and collaborating across cross‑functional teams. You have a strong foundation in electromagnetic theory, transmission lines, and advanced modeling, and you are adept at translating system requirements into actionable, measurable signoff criteria. Your expertise spans both theoretical and practical realms: you are comfortable with channel modeling, frequency and time domain analysis, and using state‑of‑the‑art simulation and measurement tools. You bring hands‑on experience in bench characterization, compliance testing, and fixture design, always striving for rigorous correlation between simulation and hardware. As a technical leader, you mentor others, drive technical reviews, and are committed to sharing your knowledge and standardizing best practices. Your disciplined approach to documentation and reproducibility ensures that learning is captured and reused. You are proactive, detail‑oriented, and thrive in dynamic environments, always seeking opportunities to optimize flows, influence architectural decisions, and deliver reliable, high‑performance solutions. Your communication skills allow you to convey complex topics clearly to both technical and non‑technical audiences, making you a valued partner to circuit, package, board, and product teams.

What You’ll Be Doing:

• Lead end-to-end SIPI for high-speed interfaces including PCI Express (Gen6/7/8), E224G, E448G, CXL (over PCIe), and other SerDes interfaces, spanning on‑die, interposer, package, PCB, connectors, and compliance fixtures.
• Drive channel modeling and correlation across time‑and frequency‑domain analysis: S‑parameters, TDR, crosstalk, ICN/ccICN, ERL/dERL, jitter/noise budgeting, equalization tradeoffs (TX/RX FFE/DFE/CTLE),eye margin simulation,and link margining.
• Own and execute SI signoff methodology for SerDes channels, including test chip package/board SIPI model extraction/model quality checks, de‑embedding, and ensuring models are bandwidth‑appropriate for target data rates.
• Partner with circuit/PHY, interposer/package, board, and product teams to diagnose bring‑up and lab issues; propose design fixes and quantify risk/benefit via simulation and measurement.
• Plan and run correlation experiments (bench characterization, compliance testing support, fixture design guidance) and document learnings as reusable design guidelines.
• Define, improve, and document SIPI flows, requirements, and checklists for internal teams and (where applicable) customers; mentor engineers and lead technical reviews.
• Provide technical leadership across programs: set priorities, identify cross‑project reuse opportunities, and influence architecture choice impacting signal integrity and power integrity.

The Impact You Will Have:

• Enable first‑pass success of high‑speed SerDes IP and system integrations by defining robust SIPI signoff criteria and delivering validated, correlated methodologies.
• Reduce schedule risk by rapidly diagnosing complex cross‑domain issues (silicon/package/board/lab) and guiding practical design changes backed by quantitative analysis.
• Raise the technical bar by mentoring others, standardizing best practices, and influencing architectural decisions for next‑generation interconnects.
• Improve product performance and reliability by ensuring thorough modeling, simulation, and correlation to hardware in diverse environments.
• Drive innovation in SIPI methodologies, enabling scalable, reusable flows across multiple programs and product lines.
• Foster a culture of collaboration and continuous improvement within the team and across partnering organizations.

What You’ll Need:

• B.S. (M.S./Ph.D. preferred) in Electrical/Electronic Engineering or related field.
• 12+ years of relevant experience in high‑speed SI/PI for SerDes links (silicon + package + board), preferably in interface IP or high‑volume product development.
• Strong fundamentals in EM, transmission lines, passive/active modeling, and statistical link analysis; comfortable translating system requirements into measurable/signoff criteria.
• Expertise with high‑speed link concepts: insertion/return loss, impedance control, mode conversion, NEXT/FEXT, jitter/noise sources, equalization, BER, etc.
• Deep expertise with modeling, simulation and EM tools (HSPICE, Keysight ADS/System Vue, Ansys HFSS/SIwave/AEDT, Cadence Sigrity, Mathworks SIMULINK) and model formats (Touchstone, IBIS‑AMI, SPICE, EM-based RLGC).
• Experience with lab correlation and measurement techniques (TDR, VNA, eye/jitter measurements, de‑embedding/fixture calibration) and working alongside validation/compliance teams.
• Proficiency in scripting/automation for flow enablement (Python preferred; MATLAB/TCL is a plus) and a disciplined approach to documentation and reproducibility.
• Demonstrated technical leadership: mentoring, design reviews, influencing cross‑functional decisions, and communicating complex topics clearly to mixed audiences.

Who You Are:

• Analytical and detail‑oriented, with a passion for tackling complex engineering challenges.
• Collaborative and communicative, able to work effectively across multi‑disciplinary teams.
• Proactive and resourceful, constantly seeking opportunities to optimize processes and drive innovation.
• Mentor and leader, committed to sharing knowledge and empowering others.
• Disciplined and organized, with a strong focus on documentation, reproducibility, and best practices.
• Adaptable, able to thrive in fast‑paced, dynamic environments.

The Team You’ll Be A Part Of:

You will join a global SerDes/PHY design team, and will interact with package and board engineering, validation, and product teams to deliver high‑performance interface IP. The team values rigorous analysis, strong correlation to hardware, and practical engineering judgment. Together, we drive innovation and enable our customers to achieve first‑pass success in advanced system environments.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non‑monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.