Senior Principal SerDes Transmitter Architect

Upscale, Inc.; Santa Clara (CA); On-site; USD 261,000 - 297,000; Full time

Job summary

Upscale, Inc. is building the world-class SerDes team to enable next-generation AI data center interconnects.

We seek a Senior Principal Engineer to lead design and development of advanced SerDes transmitter circuits, from architecture to tape-out, collaborating with cross-functional teams to deliver high-performance, power-efficient interconnect technology. The ideal candidate combines deep analog/mixed-signal expertise with hands-on experience in transmitter architectures, time-interleaved

Qualifications

• MS or PhD in Electrical Engineering or a related field with substantial experience in high-speed analog and mixed-signal IC design.
• Strong hands-on experience designing high-speed SerDes transmitters or comparable high-performance transmit circuits.
• Demonstrated expertise in transmitter clocking, high-speed DACs, output drivers, or advanced transmitter architectures.
• Strong understanding of high-speed circuit design principles including bandwidth, parasitics, jitter, noise, impedance matching, and power optimization.
• Experience with advanced CMOS processes and silicon debugging/ characterization.
• Proficiency in circuit simulation, design optimization, and silicon debug.
• Experience collaborating with layout engineers and using extracted parasitics and EM results to guide design.
• Proven ability to lead complex technical projects and deliver high-quality silicon.

Responsibilities

• Lead architecture, design, and implementation of high-speed SerDes transmitter circuits.
• Drive transmitter clock generation, distribution, and timing optimization.
• Lead high-speed DAC development including time-interleaved architectures.
• Develop calibration techniques for time-interleaved DACs.
• Design high-speed output drivers with optimized swing and impedance matching.
• Develop bandwidth-extension techniques using inductive peaking and impedance shaping.
• Apply EM simulations and extraction tools to optimize passive structures and interconnects.
• Collaborate with cross-functional teams to optimize end-to-end link performance.
• Drive silicon execution from simulations to tape-out and validation.
• Provide mentorship and establish design best practices across the SerDes team.

Skills

High-speed SerDes design

CMOS mixed-signal design

Transmitter clocking

Layout collaboration

Silicon validation

Mentorship

Education

MS or PhD in Electrical Engineering

Tools

Cadence EMX

Ansys HFSS

Job description

Upscale, Inc. is building the world-class SerDes team to enable next-generation AI data center interconnects.

We seek a Senior Principal Engineer to lead design and development of advanced SerDes transmitter circuits, from architecture to tape-out, collaborating with cross-functional teams to deliver high-performance, power-efficient interconnect technology. The ideal candidate combines deep analog/mixed-signal expertise with hands-on experience in transmitter architectures, time-interleaved