Senior SerDes Receiver & ADC Architect – 100+ GS/s

Upscale, Inc.; Kentucky; Sur place; USD 335 000 - 388 000; Plein temps

Résumé du poste

Upscale, Inc. is building a world-class SerDes engineering organization focused on ultra-high-speed connectivity for AI data centers.

We seek a technical leader to define and drive the architecture and implementation of next-generation SerDes receiver front ends and ADCs, targeting 5nm and below. You will shape receiver architecture, drive critical trade-offs across bandwidth, ENOB, jitter, and power, and collaborate across analog, DSP, clocking, and silicon validation to deliver

Qualifications

• MS or PhD in Electrical Engineering or a related field, with extensive relevant experience in high-speed analog and mixed-signal IC design.
• Demonstrated expertise in high-speed SerDes receiver architecture and circuit implementation, including ADC-based receivers.
• Significant experience designing advanced CMOS circuits in 5nm or below process technologies.
• Strong hands-on understanding of high-speed ADC architectures, sampling networks, and clocking.
• Deep understanding of bandwidth, SNR, ENOB, jitter tolerance, and power efficiency.
• Proven ability to make architecture-level decisions informed by modeling, simulations, and silicon data.
• Track record of leading complex, high-performance analog or mixed-signal designs from concept to tape-out.

Responsabilités

• Receiver Architecture: Define and drive the architecture of next-generation, ultra-high-speed SerDes receivers, including the analog front end, ADC, sampling architecture, clocking interfaces, and DSP integration.
• High-Speed ADC Development: Lead the design and optimization of ADCs targeting 100+ GS/s, addressing sampling speed, resolution, linearity, noise, and power efficiency.
• Analog Front-End Design: Drive receiver front-end development with high-bandwidth input stages, equalization, gain control, sampling networks, and core analog blocks.
• Advanced-Node Implementation: Lead circuit design and implementation in 5nm and below technologies, managing device limitations, parasitics, and layout effects.
• System-Level Optimization: Optimize bandwidth, SNR, ENOB, jitter tolerance, power consumption, and DSP complexity for best link performance.
• Clocking and Sampling: Collaborate on clock generation/distribution and timing requirements at extreme sampling rates.
• Technical Leadership: Set technical direction, mentor engineers, and resolve complex design challenges.
• Cross-Functional Collaboration: Partner with TX, clocking, DSP, physical design, package, and silicon validation teams.
• Silicon Execution: Drive feasibility studies, modeling, simulations, design reviews, and silicon characterization.
• Technology Roadmap: Shape the receiver roadmap and explore new architectures for future SerDes generations.

Connaissances

SerDes architecture

High-speed analog design

Digital signal processing

Clocking design

System-level optimization

Technical leadership

Formation

MS or PhD in Electrical Engineering

Outils

5nm CMOS

Description du poste

Upscale, Inc. is building a world-class SerDes engineering organization focused on ultra-high-speed connectivity for AI data centers.

We seek a technical leader to define and drive the architecture and implementation of next-generation SerDes receiver front ends and ADCs, targeting 5nm and below. You will shape receiver architecture, drive critical trade-offs across bandwidth, ENOB, jitter, and power, and collaborate across analog, DSP, clocking, and silicon validation to deliver