Senior SerDes & Analog IC Design Engineer

Upscale AI, Inc.; United States; On-site; USD 150,000 - 210,000; Full time

Job summary

Upscale, Inc. is seeking talented analog and mixed-signal design engineers to develop SerDes circuits and IP for next-generation AI infrastructure.

The role involves transistor-level design, simulation, and optimization of high-speed circuits, with collaboration across architecture, digital, and physical-design teams. You will contribute to design reviews, post-layout verification, silicon characterization, and automation to improve efficiency.

Qualifications

• Minimum BS/MS/PhD in Electrical Engineering or related field.
• Relevant experience in analog/mixed-signal IC design and high-speed circuits.
• Proficiency with SPICE-based simulators and standard IC design workflows.
• Familiarity with scripting languages such as Python or MATLAB.
• Strong analytical, problem-solving, and teamwork skills.

Responsibilities

• Design, simulate, and optimize analog and mixed-signal circuits for SerDes and related IP.
• Perform transistor-level circuit design, modeling, and performance analysis.
• Develop testbenches, analyze circuit behavior, and troubleshoot issues.
• Collaborate with architecture, digital, layout, and validation teams.
• Participate in design reviews and risk assessment.
• Support physical implementation, post-layout verification, and silicon characterization.
• Develop scripts to improve simulation efficiency and data analysis.
• Document design methodologies and findings.

Skills

Analog/mixed-signal design

High-speed circuit design

SPICE-based simulation

Python/MATLAB scripting

Teamwork & communication

Education

B.S./M.S./Ph.D. in Electrical Engineering

Tools

SPICE simulators

Python

MATLAB

Job description

Upscale, Inc. is seeking talented analog and mixed-signal design engineers to develop SerDes circuits and IP for next-generation AI infrastructure.

The role involves transistor-level design, simulation, and optimization of high-speed circuits, with collaboration across architecture, digital, and physical-design teams. You will contribute to design reviews, post-layout verification, silicon characterization, and automation to improve efficiency.