Senior Power Packaging Engineer – SiP/Flip-Chip

Renesas Electronics Corp.; Tempe (AZ); On-site; USD 120,000 - 180,000; Full time

Job summary

Renesas Electronics Corp. in Tempe, AZ seeks a senior package development engineer to design and advance power SiP/modules, flip-chip LGA, and multi-chip packaging architectures.

You will collaborate with OSAT/CM partners, perform DOE studies, qualify materials and processes, and drive a robust ramp-to-production with strict quality controls. The role requires 10–15 years in power packaging, strong knowledge of wafer-level packaging, and excellent cross-functional collaboration with Product,

Qualifications

• Doctorate/Masters/Bachelor’s in Engineering required.
• 10–15 years of relevant experience in package development.
• Strong interpersonal and communication skills.

Responsibilities

• Design and develop package and interconnect methods for power packaging needs.
• Qualify materials, processes and OSAT/CM suppliers.
• Collaborate with Product, Reliability, and Operations to meet schedules.
• Run DOE studies to optimize processes and establish specs.
• Ensure production ramp and tight quality controls.

Skills

Power packaging

Wafer-level packaging

Flip chip LGA

DOE / SPC

Process integration

Materials selection

Education

Doctorate/Masters/Bachelor’s in Engineering

Tools

SPC software

Statistical analysis

Job description

Renesas Electronics Corp. in Tempe, AZ seeks a senior package development engineer to design and advance power SiP/modules, flip-chip LGA, and multi-chip packaging architectures.

You will collaborate with OSAT/CM partners, perform DOE studies, qualify materials and processes, and drive a robust ramp-to-production with strict quality controls. The role requires 10–15 years in power packaging, strong knowledge of wafer-level packaging, and excellent cross-functional collaboration with Product,