Lead Power Packaging Engineer – SiP & Wafer-Level Tech

Renesas Electronics Corp.; Arizona; On-site; USD 180,000 - 240,000; Full time

Job summary

Renesas Electronics Corp. is seeking a senior Package Technology Development leader to drive R&D and NPI for AI/Datacenter infrastructure power packaging.

You will manage OSAT/CM collaborations, define roadmaps, and optimize processes to meet stringent product qualifications. The role requires 15 to 20 years in package development with emphasis on power SiP/module and wafer-level/flip-chip packaging, plus strong analytical and presentation skills.

Qualifications

• Doctorate/Masters/Bachelors in Physics, Chemistry, Mechanical, Electrical or Materials Engineering.
• 15 to 20 years of relevant experience in package development emphasizing power SiP/module, wafer level & flip-chip packaging
• Strong understanding of power SiP/modules, wafer level/flip-chip packaging methods, assembly process knowledge, qualification methods, SPC and statistical analysis software
• Knowledge of wire-bonding & multi-chip module technologies a plus.
• Strong interpersonal and communication skills.
• Strong analytical and presentation skills.

Responsibilities

• Lead package technology development and NPI, R&D, and global OSAT management.
• Develop and qualify power SiP/module packaging and interconnect methods.
• Collaborate with OSAT/CM and Product teams to optimize processes and ensure quality.
• Establish production controls and ramp-up monitoring.

Skills

Power SiP packaging

Wafer-level packaging

Flip-chip interconnects

OSAT/CM coordination

DOE process optimization

Education

PhD/MS/BS in Physics/Engineering

15–20 years package development

Tools

Statistical Analysis (SPC)

DOE software/tools

Job description

Renesas Electronics Corp. is seeking a senior Package Technology Development leader to drive R&D and NPI for AI/Datacenter infrastructure power packaging.

You will manage OSAT/CM collaborations, define roadmaps, and optimize processes to meet stringent product qualifications. The role requires 15 to 20 years in package development with emphasis on power SiP/module and wafer-level/flip-chip packaging, plus strong analytical and presentation skills.